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Date: Wed, 24 Jul 2024 15:34:10 +0100
From: Sudeep Holla <sudeep.holla@arm.com>
To: Stefan Wahren <wahrenst@gmx.net>
Cc: Frank Li <Frank.li@nxp.com>, Fabio Estevam <festevam@gmail.com>,
	peng.fan@nxp.com, peng.fan@oss.nxp.com,
	Sudeep Holla <sudeep.holla@arm.com>,
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	Pengutronix Kernel Team <kernel@pengutronix.de>,
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Subject: Re: mx93: No cache hierachy definitions for ARM cores
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In-Reply-To: <a029009c-884e-4235-a384-76090e4ccb5f@gmx.net>

On Wed, Jul 24, 2024 at 11:48:13AM +0200, Stefan Wahren wrote:
> Hi Frank,
> 
> Am 19.07.24 um 16:52 schrieb Frank Li:
> > On Thu, Jul 18, 2024 at 11:38:20PM -0300, Fabio Estevam wrote:
> > > On Wed, Jul 17, 2024 at 2:49 PM Stefan Wahren <wahrenst@gmx.net> wrote:
> > > > Hi,
> > > > today i noticed that imx93.dtsi lacks the cache definitions for the
> > > > Cortex-A55 cores:
> > > > 
> > > > cacheinfo: Unable to detect cache hierarchy for CPU 0
> > > > 
> > > > Maybe someone with more insight can add this to the imx93.dtsi file.
> > > Frank, can you help?
> > Peng:
> > 	Some informatin missed at public RM. Can you help this? I found
> > it also missed in internal tree.
> does the official ARM documentation [1] provide the missing information?
> 
> [1] - https://developer.arm.com/documentation/101051/0101

I assume you meant [2] instead of [1], as Cortex A55 and M55 are different.

--
Regards,
Sudeep

[2] https://developer.arm.com/documentation/100442/0200/