Hi Ming, Teseted all these 2 patches on top of v6.11-rc2. No "slab-out-of-bounds in cxl_setup_parent_dport" issue in cxl_test qemu env. And tested cxl_test without issue: " # meson test -C build --suite=cxl ninja: Entering directory `/root/ndctl_weiny/build' [1/48] Generating version.h with a custom command 1/11 ndctl:cxl / cxl-topology.sh OK 25.70s 2/11 ndctl:cxl / cxl-region-sysfs.sh OK 23.57s 3/11 ndctl:cxl / cxl-labels.sh OK 23.12s 4/11 ndctl:cxl / cxl-create-region.sh OK 32.80s 5/11 ndctl:cxl / cxl-xor-region.sh OK 13.92s 6/11 ndctl:cxl / cxl-events.sh OK 7.89s 7/11 ndctl:cxl / cxl-sanitize.sh OK 10.99s 8/11 ndctl:cxl / cxl-destroy-region.sh OK 11.67s 9/11 ndctl:cxl / cxl-qos-class.sh OK 11.34s 10/11 ndctl:cxl / cxl-dcd.sh SKIP 6.21s exit status 77 11/11 ndctl:cxl / cxl-security.sh OK 3.91s Ok: 10 Expected Fail: 0 Fail: 0 Unexpected Pass: 0 Skipped: 1 Timeout: 0 Full log written to /root/ndctl_weiny/build/meson-logs/testlog.txt " It's fixed. Dmesg is in attached. Best Regards, Thanks! On 2024-08-09 at 08:27:50 +0000, Li Ming wrote: > The cxl_test unit test environment on qemu always hits below call trace > with KASAN enabled: > > BUG: KASAN: slab-out-of-bounds in cxl_setup_parent_dport+0x480/0x530 [cxl_core] > Read of size 1 at addr ff110000676014f8 by task (udev-worker)/676[ 24.424403] CPU: 2 PID: 676 Comm: (udev-worker) Tainted: G O N 6.10.0-qemucxl #1 > Hardware name: QEMU Standard PC (Q35 + ICH9, 2009), BIOS edk2-20240214-2.el9 02/14/2024 > Call Trace: > > dump_stack_lvl+0xea/0x150 > print_report+0xce/0x610 > ? kasan_complete_mode_report_info+0x40/0x200 > kasan_report+0xcc/0x110 > __asan_report_load1_noabort+0x18/0x20 > cxl_setup_parent_dport+0x480/0x530 [cxl_core] > cxl_mem_probe+0x49b/0xaa0 [cxl_mem] > > cxl_test module models a CXL topology for testing, it creates some > emulated dports with platform devices in the CXL topology, so the > dport_dev of an emulated dport points to a platform device rather than a > pci device or a pci host bridge in the case. Currently, > cxl_setup_parent_dport() is used to set up RAS and AER capability on the > dport connected to the CXL memory device, but cxl_test does not support > RAS or AER functionality yet, so the fix is implementing a > __wrap_cxl_setup_parent_dport() to filter out all emulated dports, > guarantees only real dports can be handled by cxl_setup_parent_dport(). > > Fixes: f05fd10d138d ("cxl/pci: Add RCH downstream port AER register discovery") > Reported-by: Pengfei Xu > Closes: https://lore.kernel.org/linux-cxl/ZrHTBp2O+HtUe6kt@xpf.sh.intel.com/T/#t > Signed-off-by: Li Ming > --- > tools/testing/cxl/Kbuild | 1 + > tools/testing/cxl/test/mock.c | 12 ++++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/tools/testing/cxl/Kbuild b/tools/testing/cxl/Kbuild > index 030b388800f0..3d1ca9e38b1f 100644 > --- a/tools/testing/cxl/Kbuild > +++ b/tools/testing/cxl/Kbuild > @@ -14,6 +14,7 @@ ldflags-y += --wrap=cxl_dvsec_rr_decode > ldflags-y += --wrap=devm_cxl_add_rch_dport > ldflags-y += --wrap=cxl_rcd_component_reg_phys > ldflags-y += --wrap=cxl_endpoint_parse_cdat > +ldflags-y += --wrap=cxl_setup_parent_dport > > DRIVERS := ../../../drivers > CXL_SRC := $(DRIVERS)/cxl > diff --git a/tools/testing/cxl/test/mock.c b/tools/testing/cxl/test/mock.c > index 6f737941dc0e..d619672faa49 100644 > --- a/tools/testing/cxl/test/mock.c > +++ b/tools/testing/cxl/test/mock.c > @@ -299,6 +299,18 @@ void __wrap_cxl_endpoint_parse_cdat(struct cxl_port *port) > } > EXPORT_SYMBOL_NS_GPL(__wrap_cxl_endpoint_parse_cdat, CXL); > > +void __wrap_cxl_setup_parent_dport(struct device *host, struct cxl_dport *dport) > +{ > + int index; > + struct cxl_mock_ops *ops = get_cxl_mock_ops(&index); > + > + if (!ops || !ops->is_mock_port(dport->dport_dev)) > + cxl_setup_parent_dport(host, dport); > + > + put_cxl_mock_ops(index); > +} > +EXPORT_SYMBOL_NS_GPL(__wrap_cxl_setup_parent_dport, CXL); > + > MODULE_LICENSE("GPL v2"); > MODULE_IMPORT_NS(ACPI); > MODULE_IMPORT_NS(CXL); > -- > 2.40.1 >