All of lore.kernel.org
 help / color / mirror / Atom feed
From: Deepak Gupta <debug@rivosinc.com>
To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
	liwei1518@gmail.com, dbarboza@ventanamicro.com,
	zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
	andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v7 13/17] target/riscv: update `decode_save_opc` to store extra word2
Date: Thu, 22 Aug 2024 10:02:40 -0700	[thread overview]
Message-ID: <ZsdvMOyiox2pGmtg@debug.ba.rivosinc.com> (raw)
In-Reply-To: <20240822082504.3979610-14-debug@rivosinc.com>

On Thu, Aug 22, 2024 at 01:24:59AM -0700, Deepak Gupta wrote:
>Extra word 2 is stored during tcg compile and `decode_save_opc` needs
>additional argument in order to pass the value. This will be used during
>unwind to get extra information about instruction like how to massage
>exceptions. Updated all callsites as well.
>
>Signed-off-by: Deepak Gupta <debug@rivosinc.com>
>---
> target/riscv/insn_trans/trans_privileged.c.inc |  8 ++++----
> target/riscv/insn_trans/trans_rva.c.inc        |  4 ++--
> target/riscv/insn_trans/trans_rvd.c.inc        |  4 ++--
> target/riscv/insn_trans/trans_rvf.c.inc        |  4 ++--
> target/riscv/insn_trans/trans_rvh.c.inc        |  8 ++++----
> target/riscv/insn_trans/trans_rvi.c.inc        |  6 +++---
> target/riscv/insn_trans/trans_rvvk.c.inc       | 10 +++++-----
> target/riscv/insn_trans/trans_rvzacas.c.inc    |  4 ++--
> target/riscv/insn_trans/trans_rvzfh.c.inc      |  4 ++--
> target/riscv/insn_trans/trans_svinval.c.inc    |  6 +++---
> target/riscv/translate.c                       | 11 ++++++-----
> 11 files changed, 35 insertions(+), 34 deletions(-)
>
>
>@@ -1096,7 +1097,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
>         mop |= MO_ALIGN;
>     }
>
>-    decode_save_opc(ctx);
>+    decode_save_opc(ctx, RISCV_UW2_ALWAYS_STORE_AMO);
>     src1 = get_address(ctx, a->rs1, 0);
>     func(dest, src1, src2, ctx->mem_idx, mop);
>
>@@ -1110,7 +1111,7 @@ static bool gen_cmpxchg(DisasContext *ctx, arg_atomic *a, MemOp mop)
>     TCGv src1 = get_address(ctx, a->rs1, 0);
>     TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
>
>-    decode_save_opc(ctx);
>+    decode_save_opc(ctx, 0);

Note for myself. I missed this one to set `RISCV_UW2_ALWAYS_STORE_AMO`
Will wait for other feedback and fix it in v8.

>     tcg_gen_atomic_cmpxchg_tl(dest, src1, dest, src2, ctx->mem_idx, mop);
>
>     gen_set_gpr(ctx, a->rd, dest);
>-- 
>2.44.0
>


  reply	other threads:[~2024-08-22 17:02 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-22  8:24 [PATCH v7 00/17] riscv support for control flow integrity extensions Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 01/17] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 02/17] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 03/17] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 04/17] target/riscv: additional code information for sw check Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 05/17] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 06/17] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 07/17] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 08/17] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 09/17] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 10/17] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 11/17] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 12/17] target/riscv: AMO operations always raise store/AMO fault Deepak Gupta
2024-08-22  8:24 ` [PATCH v7 13/17] target/riscv: update `decode_save_opc` to store extra word2 Deepak Gupta
2024-08-22 17:02   ` Deepak Gupta [this message]
2024-08-22  8:25 ` [PATCH v7 14/17] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-22  8:25 ` [PATCH v7 15/17] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-22  8:25 ` [PATCH v7 16/17] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-22  8:25 ` [PATCH v7 17/17] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ZsdvMOyiox2pGmtg@debug.ba.rivosinc.com \
    --to=debug@rivosinc.com \
    --cc=Alistair.Francis@wdc.com \
    --cc=andy.chiu@sifive.com \
    --cc=bmeng.cn@gmail.com \
    --cc=dbarboza@ventanamicro.com \
    --cc=jim.shu@sifive.com \
    --cc=kito.cheng@sifive.com \
    --cc=liwei1518@gmail.com \
    --cc=palmer@dabbelt.com \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-riscv@nongnu.org \
    --cc=zhiwei_liu@linux.alibaba.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.