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[34.78.232.44]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-37308110436sm3247482f8f.11.2024.08.22.22.21.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Aug 2024 22:21:59 -0700 (PDT) Date: Fri, 23 Aug 2024 05:21:58 +0000 From: Sebastian Ene To: Marc Zyngier Cc: akpm@linux-foundation.org, alexghiti@rivosinc.com, ankita@nvidia.com, ardb@kernel.org, catalin.marinas@arm.com, christophe.leroy@csgroup.eu, james.morse@arm.com, vdonnefort@google.com, mark.rutland@arm.com, oliver.upton@linux.dev, rananta@google.com, ryan.roberts@arm.com, shahuang@redhat.com, suzuki.poulose@arm.com, will@kernel.org, yuzenghui@huawei.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel-team@android.com Subject: Re: [PATCH v8 5/6] KVM: arm64: Initialize the ptdump parser with stage-2 attributes Message-ID: References: <20240816123906.3683425-1-sebastianene@google.com> <20240816123906.3683425-6-sebastianene@google.com> <86plq3xoly.wl-maz@kernel.org> <8634mwy1mt.wl-maz@kernel.org> Precedence: bulk X-Mailing-List: kvmarm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8634mwy1mt.wl-maz@kernel.org> On Thu, Aug 22, 2024 at 05:15:54PM +0100, 'Marc Zyngier' via kernel-team wrote: > On Tue, 20 Aug 2024 15:20:25 +0100, > Marc Zyngier wrote: > > > > On Fri, 16 Aug 2024 13:39:05 +0100, > > Sebastian Ene wrote: > > > > > > Define a set of attributes used by the ptdump parser to display the > > > properties of a guest memory region covered by a pagetable descriptor. > > > Build a description of the pagetable levels and initialize the parser > > > with this configuration. > > > > > > Signed-off-by: Sebastian Ene > > > --- > > > arch/arm64/kvm/ptdump.c | 135 ++++++++++++++++++++++++++++++++++++++-- > > > 1 file changed, 129 insertions(+), 6 deletions(-) > > > > > > diff --git a/arch/arm64/kvm/ptdump.c b/arch/arm64/kvm/ptdump.c > > > index 52483d56be2e..79be07ec3c3c 100644 > > > --- a/arch/arm64/kvm/ptdump.c > > > +++ b/arch/arm64/kvm/ptdump.c > > > @@ -14,6 +14,51 @@ > > > #include > > > > > > > > > +#define MARKERS_LEN (2) > > > +#define KVM_PGTABLE_MAX_LEVELS (KVM_PGTABLE_LAST_LEVEL + 1) > > > + > > > +struct kvm_ptdump_guest_state { > > > + struct kvm *kvm; > > > + struct ptdump_pg_state parser_state; > > > + struct addr_marker ipa_marker[MARKERS_LEN]; > > > + struct ptdump_pg_level level[KVM_PGTABLE_MAX_LEVELS]; > > > + struct ptdump_range range[MARKERS_LEN]; > > > +}; > > > + > > > +static const struct ptdump_prot_bits stage2_pte_bits[] = { > > > + { > > > + .mask = PTE_VALID, > > > + .val = PTE_VALID, > > > + .set = " ", > > > + .clear = "F", > > > + }, { > > > + .mask = KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R | PTE_VALID, > > > + .val = KVM_PTE_LEAF_ATTR_LO_S2_S2AP_R | PTE_VALID, > > > + .set = "R", > > > + .clear = " ", > > > + }, { > > > + .mask = KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W | PTE_VALID, > > > + .val = KVM_PTE_LEAF_ATTR_LO_S2_S2AP_W | PTE_VALID, > > > + .set = "W", > > > + .clear = " ", > > > + }, { > > > + .mask = KVM_PTE_LEAF_ATTR_HI_S2_XN | PTE_VALID, > > > + .val = PTE_VALID, > > > + .set = " ", > > > + .clear = "X", > > > + }, { > > > + .mask = KVM_PTE_LEAF_ATTR_LO_S2_AF | PTE_VALID, > > > + .val = KVM_PTE_LEAF_ATTR_LO_S2_AF | PTE_VALID, > > > + .set = "AF", > > > + .clear = " ", > > > + }, { > > > + .mask = PTE_TABLE_BIT | PTE_VALID, > > > + .val = PTE_VALID, > > > + .set = "BLK", > > > + .clear = " ", > > > + }, > > > +}; > > > + > > > static int kvm_ptdump_visitor(const struct kvm_pgtable_visit_ctx *ctx, > > > enum kvm_pgtable_walk_flags visit) > > > { > > > @@ -40,15 +85,81 @@ static int kvm_ptdump_show_common(struct seq_file *m, > > > return kvm_pgtable_walk(pgtable, 0, BIT(pgtable->ia_bits), &walker); > > > } > > > > > > +static int kvm_ptdump_build_levels(struct ptdump_pg_level *level, u32 start_lvl) > > > +{ > > > + static const char * const level_names[] = {"PGD", "PUD", "PMD", "PTE"}; > > > > How about 5 level page tables, which we support since v6.8? The > > architecture uses a SL=-1 in this case, and I have the feeling this is > > going to expose in a lovely way, given that you use a u32 for > > start_level... :-/ > Hello Marc, > Talking to Oliver, I just had an epiphany: we never have a 5th level > with KVM, because we always use concatenated page tables at the start > level. So the depth is still 4 levels, but we get up to 16 pages at > level 0, and that's how we expand the IPA space from 48 to 52 bits. > Thanks for letting me know. Then it should be fine keeping that as an unisgned integer. > So by the look of it, your code should still be OK with only 4 levels. > Thanks, Seb > Apologies for leading you in the wrong direction. > > M. > > -- > Without deviation from the norm, progress is not possible. > > To unsubscribe from this group and stop receiving emails from it, send an email to kernel-team+unsubscribe@android.com. >