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From: Leo Liang <ycliang@andestech.com>
To: Jacky Chou <jacky_chou@aspeedtech.com>
Cc: <ryan_chen@aspeedtech.com>, <chiawei_wang@aspeedtech.com>,
	<BMC-SW@aspeedtech.com>, <joel@jms.id.au>,
	<joe.hershberger@ni.com>, <rfried.dev@gmail.com>,
	<trini@konsulko.com>, <sjg@chromium.org>, <kobedylan@gmail.com>,
	<u-boot@lists.denx.de>
Subject: Re: [PATCH] net: ftgmac100: Modify desc. size to cache line
Date: Mon, 9 Sep 2024 15:50:05 +0800	[thread overview]
Message-ID: <Zt6orSTxXoTh4-AS@swlinux02> (raw)
In-Reply-To: <20240628093850.3063206-1-jacky_chou@aspeedtech.com>

On Fri, Jun 28, 2024 at 05:38:50PM +0800, Jacky Chou wrote:
> The TX/RX descriptor size is 16 byte.
> When the cache line size is larger than 16 bytes, descriptors
> flushed to RAM will flush more than one descriptor.
> It is possible that it may mistakenly flush to other descriptor
> that has been updated by MAC in RAM.
> 
> To avoid this issue, align the descriptors to cache line size.
> Only one desc will be flushed or invalidated at a time.
> 
> Signed-off-by: Jacky Chou <jacky_chou@aspeedtech.com>
> ---
>  drivers/net/ftgmac100.c | 13 ++++++++++++-
>  drivers/net/ftgmac100.h |  5 +++--
>  2 files changed, 15 insertions(+), 3 deletions(-)

Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>

      reply	other threads:[~2024-09-09  7:50 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-28  9:38 [PATCH] net: ftgmac100: Modify desc. size to cache line Jacky Chou
2024-09-09  7:50 ` Leo Liang [this message]

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