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[35.187.36.109]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-42ca05c6fcesm18230355e9.3.2024.09.06.04.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Sep 2024 04:50:42 -0700 (PDT) Date: Fri, 6 Sep 2024 11:50:38 +0000 From: Mostafa Saleh To: Nicolin Chen Cc: Eric Auger , Shameerali Kolothum Thodi , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Peter Maydell , Jason Gunthorpe , Jean-Philippe Brucker , Moritz Fischer , Michael Shavit , Andrea Bolognani , "Michael S. Tsirkin" , Peter Xu Subject: Re: nested-smmuv3 topic, Sep 2024 Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=smostafa@google.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -175 X-Spam_score: -17.6 X-Spam_bar: ----------------- X-Spam_report: (-17.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, ENV_AND_HDR_SPF_MATCH=-0.5, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: ytrmfZ8Hso8+ Hi Nicolin, On Thu, Sep 05, 2024 at 01:26:20AM -0700, Nicolin Chen wrote: > Hi all, > > Hope I didn't miss anybody who is related to the topic. Please, > feel free to add! > > <--- Background ---> > As some of you know, there is an ongoing effort for nested-smmuv3 > support in QEMU on ARM, working with the kernel IOMMUFD uAPIs: > [Nesting for vSTE] > https://lore.kernel.org/linux-iommu/0-v2-621370057090+91fec-smmuv3_nesting_jgg@nvidia.com/ > [Nesting for invalidations] > https://lore.kernel.org/linux-iommu/cover.1724776335.git.nicolinc@nvidia.com/ > > The kernel patches are still under review. Jason and I are hoping > them to get merged at next cycle for v6.13, which means the QEMU > patches might start a review process as early as Nov/Dec? > > That being said, I think we are way behind the point that patches > can get reviewed: most of the QEMU patches on my branches weren't > touched very often, but merely updated to the latest kernel uAPIs > for verification. So, I feel this might be a good point to gather > folks together to discuss about the possible timeline and ask for > help. I think this would potentially help folks who are going to > attend the KVM forum (or LPC) to carry out a discussion. (Sorry, > I won't make it due to some conflict..) > > <-- Task Breakdown ---> > I previously sent a RFCv1 series collecting comments/suggestions, > for multi-vSMMU instance design in ARM Virt code: > https://lore.kernel.org/qemu-devel/cover.1719361174.git.nicolinc@nvidia.com/ > (And thanks again for all the inputs!) > > The main takeaway from the discussion is to > 1) Turn the vSMMU module into a pluggable one, like intel-iommu > 2) Move the per-SMMU pxb bus and device auto-assign into libvirt > > Apart from the multi-vSMMU thing, there's basic nesting series: > 0) Keep updating to the latest kernel uAPIs to support nesting > > I was trying to do all these three, but apparently too ambitious. > The kernel side of work is still taking a lot of my bandwidth. So > far I had almost-zero progress on task (1) and completely-zero on > task (2). > > <-- Help Needed ---> > So, I'm wondering if anyone(s) might have some extra bandwidth in > the following months helping these two tasks, either of which can > be a standalone project I think. I don’t have plans to work on qemu in the next months, most of my upstream focus will be on pKVM SMMUv3 support[1] in Linux which might overlap with some of the vSMMU work but in the kernel side. Otherwise, I’d be happy to review patches. [1] https://lore.kernel.org/kvmarm/20230201125328.2186498-1-jean-philippe@linaro.org/ Thanks, Mostafa > > For task (0), I think I can keep updating the uAPI part, although > it'd need some help for reviews, which I was hoping to occur after > Intel sends the QEMU nesting backend patches. Once we know how big > the rework is going to be, we may need to borrow some help at that > point once again.. > > Thank you > Nicolin