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[35.189.131.103]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-719090ae07bsm2267726b3a.163.2024.09.10.23.08.18 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 Sep 2024 23:08:19 -0700 (PDT) Date: Wed, 11 Sep 2024 15:08:07 +0900 From: Dominique Martinet To: Frieder Schrempf Cc: Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Vinod Koul , Adam Ford , Lucas Stach , Marco Felsch , Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= Subject: Re: [PATCH 0/2] Extending PLL LUT for i.MX8MP Samsung HDMI PHY Message-ID: References: <20240910181544.214797-1-frieder@fris.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240910_230822_972579_00DD47C7 X-CRM114-Status: GOOD ( 13.00 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org Dominique Martinet wrote on Wed, Sep 11, 2024 at 09:23:31AM +0900: > so if I find some time I'll whip some loop to check all other values... There were more differences than I thought there'd be (see diff below) they're all minor enough to probably not care, but your script finds exact values for them so it might be worth updating the regs if we keep the table... (OTOH these seem to work, and "if it works don't touch it" -- I have no further opinion now I've checked, curiosity is sated) Might want to just check 154000000 though, reg6's 0x80 was not set so SDC was disabled? and it'd get the integer fraction (153600000) instead if I understand this correctly --------- diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index a5ad51425ee3..72facc7bd045 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -73,7 +73,7 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 24024000, .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, }, { - .pixclk = 25175000, + .pixclk = 25177981, .pll_div_regs = { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, }, { .pixclk = 26750000, @@ -82,16 +82,16 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 27027000, .pll_div_regs = { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, }, { - .pixclk = 29500000, + .pixclk = 29487500, .pll_div_regs = { 0xd1, 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 }, }, { - .pixclk = 30750000, + .pixclk = 30729661, .pll_div_regs = { 0xd1, 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 }, }, { - .pixclk = 30888000, + .pixclk = 30848949, .pll_div_regs = { 0xd1, 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 }, }, { - .pixclk = 33750000, + .pixclk = 33731250, .pll_div_regs = { 0xd1, 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 }, }, { .pixclk = 35000000, @@ -106,13 +106,13 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 44500000, .pll_div_regs = { 0xd1, 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 }, }, { - .pixclk = 47000000, + .pixclk = 47005000, .pll_div_regs = { 0xd1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 }, }, { - .pixclk = 47500000, + .pixclk = 47502000, .pll_div_regs = { 0xd1, 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 }, }, { - .pixclk = 50349650, + .pixclk = 50355924, .pll_div_regs = { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, }, { .pixclk = 53250000, @@ -124,16 +124,16 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 54054000, .pll_div_regs = { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, }, { - .pixclk = 59000000, + .pixclk = 58975000, .pll_div_regs = { 0xd1, 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 }, }, { - .pixclk = 59340659, + .pixclk = 59264777, .pll_div_regs = { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, }, { - .pixclk = 61500000, + .pixclk = 61459322, .pll_div_regs = { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, }, { - .pixclk = 63500000, + .pixclk = 63437500, .pll_div_regs = { 0xd1, 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 }, }, { .pixclk = 67500000, @@ -145,25 +145,25 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 72072000, .pll_div_regs = { 0xd1, 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, }, { - .pixclk = 74176000, + .pixclk = 74175824, .pll_div_regs = { 0xd1, 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 }, }, { .pixclk = 74250000, .pll_div_regs = { 0xd1, 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 }, }, { - .pixclk = 78500000, + .pixclk = 78487500, .pll_div_regs = { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, }, { - .pixclk = 82000000, + .pixclk = 81945763, .pll_div_regs = { 0xd1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, }, { - .pixclk = 82500000, + .pixclk = 82486555, .pll_div_regs = { 0xd1, 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 }, }, { - .pixclk = 89000000, + .pixclk = 89075000, .pll_div_regs = { 0xd1, 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 }, }, { - .pixclk = 90000000, + .pixclk = 89950000, .pll_div_regs = { 0xd1, 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 }, }, { .pixclk = 94000000, @@ -178,7 +178,7 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 99000000, .pll_div_regs = { 0xd1, 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 }, }, { - .pixclk = 100699300, + .pixclk = 100711847, .pll_div_regs = { 0xd1, 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, }, { .pixclk = 102500000, @@ -196,16 +196,16 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 108108000, .pll_div_regs = { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, }, { - .pixclk = 118000000, + .pixclk = 117950000, .pll_div_regs = { 0xd1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, }, { - .pixclk = 123000000, + .pixclk = 122918644, .pll_div_regs = { 0xd1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, }, { - .pixclk = 127000000, + .pixclk = 126875000, .pll_div_regs = { 0xd1, 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 }, }, { - .pixclk = 135000000, + .pixclk = 134925000, .pll_div_regs = { 0xd1, 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 }, }, { .pixclk = 135580000, @@ -214,20 +214,20 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 137520000, .pll_div_regs = { 0xd1, 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 }, }, { - .pixclk = 138750000, + .pixclk = 138658397, .pll_div_regs = { 0xd1, 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d }, }, { - .pixclk = 140000000, + .pixclk = 140040000, .pll_div_regs = { 0xd1, 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, }, { - .pixclk = 148352000, + .pixclk = 148265128, .pll_div_regs = { 0xd1, 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, }, { - .pixclk = 148500000, + .pixclk = 148396403, .pll_div_regs = { 0xd1, 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 }, }, { .pixclk = 154000000, - .pll_div_regs = { 0xd1, 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 }, + .pll_div_regs = { 0xd1, 0x40, 0x18, 0x83, 0x01, 0x80, 0x40 }, }, { .pixclk = 157000000, .pll_div_regs = { 0xd1, 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 }, @@ -268,10 +268,10 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 254000000, .pll_div_regs = { 0xd1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, }, { - 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[35.189.131.103]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-719090ae07bsm2267726b3a.163.2024.09.10.23.08.18 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 Sep 2024 23:08:19 -0700 (PDT) Date: Wed, 11 Sep 2024 15:08:07 +0900 From: Dominique Martinet To: Frieder Schrempf Cc: Kishon Vijay Abraham I , linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Vinod Koul , Adam Ford , Lucas Stach , Marco Felsch , Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= Subject: Re: [PATCH 0/2] Extending PLL LUT for i.MX8MP Samsung HDMI PHY Message-ID: References: <20240910181544.214797-1-frieder@fris.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Dominique Martinet wrote on Wed, Sep 11, 2024 at 09:23:31AM +0900: > so if I find some time I'll whip some loop to check all other values... There were more differences than I thought there'd be (see diff below) they're all minor enough to probably not care, but your script finds exact values for them so it might be worth updating the regs if we keep the table... (OTOH these seem to work, and "if it works don't touch it" -- I have no further opinion now I've checked, curiosity is sated) Might want to just check 154000000 though, reg6's 0x80 was not set so SDC was disabled? and it'd get the integer fraction (153600000) instead if I understand this correctly --------- diff --git a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c index a5ad51425ee3..72facc7bd045 100644 --- a/drivers/phy/freescale/phy-fsl-samsung-hdmi.c +++ b/drivers/phy/freescale/phy-fsl-samsung-hdmi.c @@ -73,7 +73,7 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 24024000, .pll_div_regs = { 0xd1, 0x50, 0xf1, 0x99, 0x02, 0x80, 0x40 }, }, { - .pixclk = 25175000, + .pixclk = 25177981, .pll_div_regs = { 0xd1, 0x54, 0xfc, 0xcc, 0x91, 0x80, 0x40 }, }, { .pixclk = 26750000, @@ -82,16 +82,16 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 27027000, .pll_div_regs = { 0xd1, 0x5a, 0xf2, 0xfd, 0x0c, 0x80, 0x40 }, }, { - .pixclk = 29500000, + .pixclk = 29487500, .pll_div_regs = { 0xd1, 0x62, 0xf4, 0x95, 0x08, 0x80, 0x40 }, }, { - .pixclk = 30750000, + .pixclk = 30729661, .pll_div_regs = { 0xd1, 0x66, 0xf4, 0x82, 0x01, 0x88, 0x45 }, }, { - .pixclk = 30888000, + .pixclk = 30848949, .pll_div_regs = { 0xd1, 0x66, 0xf4, 0x99, 0x18, 0x88, 0x45 }, }, { - .pixclk = 33750000, + .pixclk = 33731250, .pll_div_regs = { 0xd1, 0x70, 0xf4, 0x82, 0x01, 0x80, 0x40 }, }, { .pixclk = 35000000, @@ -106,13 +106,13 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 44500000, .pll_div_regs = { 0xd1, 0x5c, 0x92, 0x98, 0x11, 0x84, 0x41 }, }, { - .pixclk = 47000000, + .pixclk = 47005000, .pll_div_regs = { 0xd1, 0x62, 0x94, 0x95, 0x82, 0x80, 0x40 }, }, { - .pixclk = 47500000, + .pixclk = 47502000, .pll_div_regs = { 0xd1, 0x63, 0x96, 0xa1, 0x82, 0x80, 0x40 }, }, { - .pixclk = 50349650, + .pixclk = 50355924, .pll_div_regs = { 0xd1, 0x54, 0x7c, 0xc3, 0x8f, 0x80, 0x40 }, }, { .pixclk = 53250000, @@ -124,16 +124,16 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 54054000, .pll_div_regs = { 0xd1, 0x5a, 0x72, 0xfd, 0x0c, 0x80, 0x40 }, }, { - .pixclk = 59000000, + .pixclk = 58975000, .pll_div_regs = { 0xd1, 0x62, 0x74, 0x95, 0x08, 0x80, 0x40 }, }, { - .pixclk = 59340659, + .pixclk = 59264777, .pll_div_regs = { 0xd1, 0x62, 0x74, 0xdb, 0x52, 0x88, 0x47 }, }, { - .pixclk = 61500000, + .pixclk = 61459322, .pll_div_regs = { 0xd1, 0x66, 0x74, 0x82, 0x01, 0x88, 0x45 }, }, { - .pixclk = 63500000, + .pixclk = 63437500, .pll_div_regs = { 0xd1, 0x69, 0x74, 0x89, 0x08, 0x80, 0x40 }, }, { .pixclk = 67500000, @@ -145,25 +145,25 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 72072000, .pll_div_regs = { 0xd1, 0x5a, 0x52, 0xfd, 0x0c, 0x80, 0x40 }, }, { - .pixclk = 74176000, + .pixclk = 74175824, .pll_div_regs = { 0xd1, 0x5d, 0x58, 0xdb, 0xA2, 0x88, 0x41 }, }, { .pixclk = 74250000, .pll_div_regs = { 0xd1, 0x5c, 0x52, 0x90, 0x0d, 0x84, 0x41 }, }, { - .pixclk = 78500000, + .pixclk = 78487500, .pll_div_regs = { 0xd1, 0x62, 0x54, 0x87, 0x01, 0x80, 0x40 }, }, { - .pixclk = 82000000, + .pixclk = 81945763, .pll_div_regs = { 0xd1, 0x66, 0x54, 0x82, 0x01, 0x88, 0x45 }, }, { - .pixclk = 82500000, + .pixclk = 82486555, .pll_div_regs = { 0xd1, 0x67, 0x54, 0x88, 0x01, 0x90, 0x49 }, }, { - .pixclk = 89000000, + .pixclk = 89075000, .pll_div_regs = { 0xd1, 0x70, 0x54, 0x84, 0x83, 0x80, 0x40 }, }, { - .pixclk = 90000000, + .pixclk = 89950000, .pll_div_regs = { 0xd1, 0x70, 0x54, 0x82, 0x01, 0x80, 0x40 }, }, { .pixclk = 94000000, @@ -178,7 +178,7 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 99000000, .pll_div_regs = { 0xd1, 0x52, 0x32, 0x82, 0x01, 0x88, 0x47 }, }, { - .pixclk = 100699300, + .pixclk = 100711847, .pll_div_regs = { 0xd1, 0x54, 0x3c, 0xc3, 0x8f, 0x80, 0x40 }, }, { .pixclk = 102500000, @@ -196,16 +196,16 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 108108000, .pll_div_regs = { 0xd1, 0x5a, 0x32, 0xfd, 0x0c, 0x80, 0x40 }, }, { - .pixclk = 118000000, + .pixclk = 117950000, .pll_div_regs = { 0xd1, 0x62, 0x34, 0x95, 0x08, 0x80, 0x40 }, }, { - .pixclk = 123000000, + .pixclk = 122918644, .pll_div_regs = { 0xd1, 0x66, 0x34, 0x82, 0x01, 0x88, 0x45 }, }, { - .pixclk = 127000000, + .pixclk = 126875000, .pll_div_regs = { 0xd1, 0x69, 0x34, 0x89, 0x08, 0x80, 0x40 }, }, { - .pixclk = 135000000, + .pixclk = 134925000, .pll_div_regs = { 0xd1, 0x70, 0x34, 0x82, 0x01, 0x80, 0x40 }, }, { .pixclk = 135580000, @@ -214,20 +214,20 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 137520000, .pll_div_regs = { 0xd1, 0x72, 0x38, 0x99, 0x10, 0x85, 0x41 }, }, { - .pixclk = 138750000, + .pixclk = 138658397, .pll_div_regs = { 0xd1, 0x73, 0x35, 0x88, 0x05, 0x90, 0x4d }, }, { - .pixclk = 140000000, + .pixclk = 140040000, .pll_div_regs = { 0xd1, 0x75, 0x36, 0xa7, 0x90, 0x80, 0x40 }, }, { - .pixclk = 148352000, + .pixclk = 148265128, .pll_div_regs = { 0xd1, 0x7b, 0x35, 0xdb, 0x39, 0x90, 0x45 }, }, { - .pixclk = 148500000, + .pixclk = 148396403, .pll_div_regs = { 0xd1, 0x7b, 0x35, 0x84, 0x03, 0x90, 0x45 }, }, { .pixclk = 154000000, - .pll_div_regs = { 0xd1, 0x40, 0x18, 0x83, 0x01, 0x00, 0x40 }, + .pll_div_regs = { 0xd1, 0x40, 0x18, 0x83, 0x01, 0x80, 0x40 }, }, { .pixclk = 157000000, .pll_div_regs = { 0xd1, 0x41, 0x11, 0xa7, 0x14, 0x80, 0x40 }, @@ -268,10 +268,10 @@ static const struct phy_config phy_pll_cfg[] = { .pixclk = 254000000, .pll_div_regs = { 0xd1, 0x69, 0x14, 0x89, 0x08, 0x80, 0x40 }, }, { - .pixclk = 277500000, + .pixclk = 277316794, .pll_div_regs = { 0xd1, 0x73, 0x15, 0x88, 0x05, 0x90, 0x4d }, }, { - .pixclk = 297000000, + .pixclk = 296792806, .pll_div_regs = { 0xd1, 0x7b, 0x15, 0x84, 0x03, 0x90, 0x45 }, }, }; ------------- -- Dominique