From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9290FCF3962 for ; Thu, 19 Sep 2024 19:00:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=pm9LHimE822xVhiuGJtHS2j4sVrbi1IFvTW3CqLHmBA=; b=PRKfz1zSO8I7v06LPty/rXmaQG pw7gWs5jzZ9xd0THMZof+HX2bs4Po4wJK1lnvMZBDwZPMCAzyME/Z8M2FuaVu7lvKIgpP+OB0cLNm wH8mpFKwCON9My47Dp50TIzd+iHdYnLu1cbnjC8OxK1tvxM4MG044819x1/KqzG3lW0OUIEnYx7NR ge6YlPJgj9a8XcHtebVTLffSwniun6WTCltw9f8J0/k3tjTTIB0+6U64b8dZu0rnGK3z6MxAChXFZ oZehfPJmZoQUWmApbHU5f0H4/wc2zReddeyYc+l/dSZ/7PAq8LYHnTn0hl+zxk6kJ+aLE3K+Tknw8 3QmYtX6g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1srMNj-0000000As7X-2ctC; Thu, 19 Sep 2024 18:59:59 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1srMMb-0000000ArxN-1hqN for linux-arm-kernel@lists.infradead.org; Thu, 19 Sep 2024 18:58:50 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by dfw.source.kernel.org (Postfix) with ESMTP id 1E4585C5A64; Thu, 19 Sep 2024 18:58:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0B6BBC4CEC4; Thu, 19 Sep 2024 18:58:44 +0000 (UTC) Date: Thu, 19 Sep 2024 19:58:42 +0100 From: Catalin Marinas To: Yicong Yang Cc: Will Deacon , yangyicong@hisilicon.com, maz@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, oliver.upton@linux.dev, broonie@kernel.org, ryan.roberts@arm.com, linuxarm@huawei.com, jonathan.cameron@huawei.com, shameerali.kolothum.thodi@huawei.com, prime.zeng@hisilicon.com, xuwei5@huawei.com, wangkefeng.wang@huawei.com Subject: Re: [PATCH v2 1/2] arm64: Add support for FEAT_HAFT Message-ID: References: <20240814092333.7727-1-yangyicong@huawei.com> <20240814092333.7727-2-yangyicong@huawei.com> <20240820161822.GC28750@willie-the-truck> <6a240d93-f818-c486-2603-05f651658277@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6a240d93-f818-c486-2603-05f651658277@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240919_115849_536091_E519D6F5 X-CRM114-Status: GOOD ( 34.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Aug 29, 2024 at 02:29:41PM +0800, Yicong Yang wrote: > On 2024/8/21 0:18, Will Deacon wrote: > > On Wed, Aug 14, 2024 at 05:23:32PM +0800, Yicong Yang wrote: > >> +static void cpu_enable_haft(struct arm64_cpu_capabilities const *cap) > >> +{ > >> + sysreg_clear_set_s(SYS_TCR2_EL1, 0, TCR2_EL1x_HAFT); > >> + isb(); > >> + local_flush_tlb_all(); > >> +} > > > > As this isn't a per-TTBR enable, should we be initialising the kernel > > table entries in TTBR1 as YOUNG to avoid potential races with the > > hardware update? It looks like the bit is ignored on CPUs without HAFT, > > so we can just do this unconditionally. > > I'm a bit uncertain about the race here, is it because of the access fault > or the inconsistent observation of table entries' AF status when enable the > HAFT? and... Linux doesn't use this mechanism on kernel page tables. The hardware update of the access bit is atomic and, while it could race with a non-atomic entry update, it shouldn't matter since no-one checks this bit. However, I'd still set the AF bit when creating the kernel page table, it saves the hardware from having to update them at run-time. > > At the very least, we should be able to enable HAFT in __cpu_setup(), > > like we do for HA. > > > > ...if we enable this in __cpu_setup() as suggested we should have no race problem, > since this is enabled before MMU on? I suspect Will was referring to the actual page tables. But it makes sense to enable this in __cpu_setup(), it saves us from having to do the TLBI. > > It's a bit of a pity that we can't handle this mismatch. After all, > > access flag data is imprecise (unlike the dirty bit) and so you could > > envisage a mechanism for falling back to leaf-level AF at runtime rather > > than refusing to online a CPU. > > ok. I suppose enable this should be ok if no users. So it's possible to just > try to enable this at each CPU's startup, but don't advertise this feature to > the upper users if not all the CPUs in the system support this. This won't > affect leaf-level AF since leaf-level AF has its own detection and enabling > and doesn't depend on HAFT. Yes, I think this should work as long as arch_has_hw_pte_young() returns false if one of the CPUs doesn't support it. I had a quick grep through the kernel and all (most?) cases where the non-leaf pmd is checked or the AF bit cleared are conditional on should_clear_pmd_young(). Personally I'd have introduced pmd_nonleaf_young() etc. functions in the core code to make it more explicit. I guess, if we really want, we could add a VM_WARN_ON if pmd_young() or pmdp_test_and_clear_young() is called on a non-leaf pmd and FEAT_HAFT is disabled. -- Catalin