From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8EB27CEACF3 for ; Wed, 2 Oct 2024 17:11:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=naxQjLqUpAu24KMDraD3b9Ebra3WIh3ycvkzDSNgP0A=; b=dDz9608+qKdxw38A8MLTRcAnpU dj8m0YlBztBTZn3qL2pHcOhZNirnUnycKw+CuoH5wNz/MlD1zhfvx2D/FUJsTPdrQzls+C5/uxxv0 tHQYk5kDWrR+BOzDateH7JY/YZznmfUaPa8OAtbJ9PVEW0qMGgm2NyjHYxwn1CYBWdRZBt4YZFQ3s QREUc1p2SpFzQpf1fk/QL9Q2CCxywocgRW2xDpJCQRuZBnZQ8vZ2vp64bCXwcjnjTrAwrjfvB56tE RYrdq/r/cyf0LY2t8oWZmYdJkERgt1xcbOFSQAaUG3Y1bqknTIrBreWDX9ts0PSyUEyZgMu0tkglo yqGP4bIQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1sw2sg-000000071yX-0zfD; Wed, 02 Oct 2024 17:11:18 +0000 Received: from nyc.source.kernel.org ([147.75.193.91]) by bombadil.infradead.org with esmtps (Exim 4.98 #2 (Red Hat Linux)) id 1sw2rR-000000071q0-00Zn for linux-arm-kernel@lists.infradead.org; Wed, 02 Oct 2024 17:10:02 +0000 Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by nyc.source.kernel.org (Postfix) with ESMTP id 622B7A41982; Wed, 2 Oct 2024 17:09:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1CB31C4CEC2; Wed, 2 Oct 2024 17:09:57 +0000 (UTC) Date: Wed, 2 Oct 2024 18:09:55 +0100 From: Catalin Marinas To: Kristina Martsenko Cc: "linux-arm-kernel@lists.infradead.org" , Will Deacon , Mark Rutland , Robin Murphy , Marc Zyngier Subject: Re: [PATCH 3/5] arm64: mops: Document booting requirement for HCR_EL2.MCE2 Message-ID: References: <20240930161051.3777828-1-kristina.martsenko@arm.com> <20240930161051.3777828-4-kristina.martsenko@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241002_101001_125124_87C98C9A X-CRM114-Status: GOOD ( 21.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Oct 02, 2024 at 02:31:47PM +0100, Kristina Martsenko wrote: > On 02/10/2024 11:38, Catalin Marinas wrote: > > On Mon, Sep 30, 2024 at 05:10:49PM +0100, Kristina Martsenko wrote: > >> diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst > >> index b57776a68f15..db46af5b9f0f 100644 > >> --- a/Documentation/arch/arm64/booting.rst > >> +++ b/Documentation/arch/arm64/booting.rst > >> @@ -385,6 +385,9 @@ Before jumping into the kernel, the following conditions must be met: > >> > >> - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1. > >> > >> + - HCRX_EL2.MCE2 (bit 10) must be initialised to 0b1. The exception > >> + handler must set PSTATE.SS to 0b0. > > > > That's a booting document, do we need to specify the single-step > > exception? > > A hypervisor can't just set MCE2 at kernel boot without also implementing an > exception handler for MOPS exceptions. The handler needs to implement the > algorithm from the Arm ARM, and in addition the kernel needs it to also clear > SS so that breakpoints/watchpoints (and KGDB single stepping) work as expected. > Is there a better place to specify this? Not sure, maybe a short mops.rst document describing the exception handling needs for a hypervisor running Linux (well, if it's just a couple of sentences, we might as well keep them in booting.rst). In a mops.rst you could add more lines explaining the exception handling and the reasoning behind PSTATE.SS. In booting.rst you can just refer mops.rst. I'm trying to remember the discussions that lead to such requirement. Basically the worry is that the vCPU the kernel is running on migrates to another physical CPU with a different MOPS implementation and triggers a fault into the kernel. The kernel may not be able to handle the fault itself, hence setting MCE2 to force trapping to EL2. This is all fine but the requirement for the hypervisor to clear PSTATE.SS feels a bit strange. Doesn't it break the kernel's state machine (or gdb's) if, suddenly, it no longer traps the next instruction? -- Catalin