All of lore.kernel.org
 help / color / mirror / Atom feed
From: Zhao Liu <zhao1.liu@intel.com>
To: Chao Gao <chao.gao@intel.com>
Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, jmattson@google.com,
	pawan.kumar.gupta@linux.intel.com, jon@nutanix.com
Subject: Re: [PATCH] target/i386: Add more features enumerated by CPUID.7.2.EDX
Date: Wed, 9 Oct 2024 15:47:13 +0800	[thread overview]
Message-ID: <ZwY1AeJPlrniISB1@intel.com> (raw)
In-Reply-To: <20240919051011.118309-1-chao.gao@intel.com>

On Thu, Sep 19, 2024 at 01:10:11PM +0800, Chao Gao wrote:
> Date: Thu, 19 Sep 2024 13:10:11 +0800
> From: Chao Gao <chao.gao@intel.com>
> Subject: [PATCH] target/i386: Add more features enumerated by CPUID.7.2.EDX
> X-Mailer: git-send-email 2.46.1
> 
> Following 5 bits in CPUID.7.2.EDX are supported by KVM. Add their
> supports in QEMU. Each of them indicates certain bits of IA32_SPEC_CTRL
> are supported. Those bits can control CPU speculation behavior which can
> be used to defend against side-channel attacks.
> 
> bit0: intel-psfd
>   if 1, indicates bit 7 of the IA32_SPEC_CTRL MSR is supported. Bit 7 of
>   this MSR disables Fast Store Forwarding Predictor without disabling
>   Speculative Store Bypass
> 
> bit1: ipred-ctrl
>   If 1, indicates bits 3 and 4 of the IA32_SPEC_CTRL MSR are supported.
>   Bit 3 of this MSR enables IPRED_DIS control for CPL3. Bit 4 of this
>   MSR enables IPRED_DIS control for CPL0/1/2
> 
> bit2: rrsba-ctrl
>   If 1, indicates bits 5 and 6 of the IA32_SPEC_CTRL MSR are supported.
>   Bit 5 of this MSR disables RRSBA behavior for CPL3. Bit 6 of this MSR
>   disables RRSBA behavior for CPL0/1/2
> 
> bit3: ddpd-u
>   If 1, indicates bit 8 of the IA32_SPEC_CTRL MSR is supported. Bit 8 of
>   this MSR disables Data Dependent Prefetcher.
> 
> bit4: bhi-ctrl
>   if 1, indicates bit 10 of the IA32_SPEC_CTRL MSR is supported. Bit 10
>   of this MSR enables BHI_DIS_S behavior.
> 
> Signed-off-by: Chao Gao <chao.gao@intel.com>
> ---
>  target/i386/cpu.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 85ef7452c0..18ba958f46 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -1148,8 +1148,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
>      [FEAT_7_2_EDX] = {
>          .type = CPUID_FEATURE_WORD,
>          .feat_names = {
> -            NULL, NULL, NULL, NULL,
> -            NULL, "mcdt-no", NULL, NULL,
> +            "intel-psfd", "ipred-ctrl", "rrsba-ctrl", "ddpd-u",
> +            "bhi-ctrl", "mcdt-no", NULL, NULL,

IIUC, these bits depend on "spec-ctrl", which indicates the presence of
IA32_SPEC_CTRL.

Then I think we'd better add dependencies in feature_dependencies[].

-Zhao

>              NULL, NULL, NULL, NULL,
>              NULL, NULL, NULL, NULL,
>              NULL, NULL, NULL, NULL,
> -- 
> 2.46.1
> 
> 


  reply	other threads:[~2024-10-09  7:32 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-19  5:10 [PATCH] target/i386: Add more features enumerated by CPUID.7.2.EDX Chao Gao
2024-10-09  7:47 ` Zhao Liu [this message]
2024-10-09  8:12   ` Chao Gao
2024-10-10 13:17     ` Paolo Bonzini
2024-10-11  4:22       ` Zhao Liu
2024-10-10 13:18 ` Paolo Bonzini

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=ZwY1AeJPlrniISB1@intel.com \
    --to=zhao1.liu@intel.com \
    --cc=chao.gao@intel.com \
    --cc=jmattson@google.com \
    --cc=jon@nutanix.com \
    --cc=pawan.kumar.gupta@linux.intel.com \
    --cc=pbonzini@redhat.com \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.