Re: [PATCH v3 2/7] target/i386: Add RAS feature bits on EPYC CPU models

[Zhao Liu <zhao1.liu@intel.com>]

(+John)

Hi Babu,

This patch is fine for me.

However, users recently reported an issue with SUCCOR support on AMD
hosts: https://gitlab.com/qemu-project/qemu/-/issues/2571.

Could you please double check and clarify that issue on AMD host?

Thanks,
Zhao

On Thu, Oct 24, 2024 at 05:18:20PM -0500, Babu Moger wrote:
> Date: Thu, 24 Oct 2024 17:18:20 -0500
> From: Babu Moger <babu.moger@amd.com>
> Subject: [PATCH v3 2/7] target/i386: Add RAS feature bits on EPYC CPU models
> X-Mailer: git-send-email 2.34.1
> 
> Add the support for following RAS features bits on AMD guests.
> 
> SUCCOR: Software uncorrectable error containment and recovery capability.
> 	The processor supports software containment of uncorrectable errors
> 	through context synchronizing data poisoning and deferred error
> 	interrupts.
> 
> McaOverflowRecov: MCA overflow recovery support.
> 
> Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> v3: No changes
> 
> v2: Added reviewed by from Zhao.
> ---
>  target/i386/cpu.c | 30 ++++++++++++++++++++++++++++++
>  1 file changed, 30 insertions(+)