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b=QdpYHD9Xj26PZO6HBFMyHy/qTwso8JZAVcyO2RRxmeUv MLYpUMJPyL3HmqYtvD5NlkzqF54ToAkKkfs9PWVlsoRdO0d4hI2nt5anciNf5dXF VELatzwipxYEl/ZOdKRSAVAyEC3eJbuhD7biBbXsKWQeorQL5DKLTmAxKYKy+vU+ Z826PqEIBd4pZq0LG8BWSUETOZkGVzeQpjQWKSQDDXike4zxi65ycD8fz8VrM5La QbyOBn9blwwknLL3GFGnzoJPXhPa8cwwLEVo4UV70Jfq0eVWnX59Tam4FYc37jL/ H3vcVj/7/GDQALAbujebG1i9BoJWkNSCNU5Mo4efYQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeftddrvdehgedgjeduucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdggtfgfnhhsuhgsshgtrhhisggvpdfu rfetoffkrfgpnffqhgenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnh htshculddquddttddmnecujfgurhepfffhvfevuffkfhggtggujgesghdtreertddtjeen ucfhrhhomhepofgrrhgvkhcuofgrrhgtiiihkhhofihskhhiqdfikphrvggtkhhiuceomh grrhhmrghrvghksehinhhvihhsihgslhgvthhhihhnghhslhgrsgdrtghomheqnecuggft rfgrthhtvghrnhepgfduleetfeevhfefheeiteeliefhjefhleduveetteekveettddvge euteefjedunecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhho mhepmhgrrhhmrghrvghksehinhhvihhsihgslhgvthhhihhnghhslhgrsgdrtghomhdpnh gspghrtghpthhtohepiedpmhhouggvpehsmhhtphhouhhtpdhrtghpthhtoheprhhoghgv rhdrphgruhestghithhrihigrdgtohhmpdhrtghpthhtohepgigvnhdquggvvhgvlheslh hishhtshdrgigvnhhprhhojhgvtghtrdhorhhgpdhrtghpthhtohepjhgsvghulhhitghh sehsuhhsvgdrtghomhdprhgtphhtthhopegrnhgurhgvfidrtghoohhpvghrfeestghith hrihigrdgtohhmpdhrtghpthhtohepgigvnhhprhhojhgvtghtseihmhihrdgsvgdprhgt phhtthhopegufihmfiesrghmrgiiohhnrdgtohdruhhk X-ME-Proxy: Feedback-ID: i1568416f:Fastmail Date: Sat, 19 Oct 2024 05:23:38 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Roger Pau Monne Cc: xen-devel@lists.xenproject.org, Jan Beulich , Andrew Cooper , Willi Junga , David Woodhouse Subject: Re: [PATCH] x86/io-apic: fix directed EOI when using AMd-Vi interrupt remapping Message-ID: References: <20241018080813.45759-1-roger.pau@citrix.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="+AprsNGlh2aM16SR" Content-Disposition: inline In-Reply-To: <20241018080813.45759-1-roger.pau@citrix.com> --+AprsNGlh2aM16SR Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Sat, 19 Oct 2024 05:23:38 +0200 From: Marek =?utf-8?Q?Marczykowski-G=C3=B3recki?= To: Roger Pau Monne Cc: xen-devel@lists.xenproject.org, Jan Beulich , Andrew Cooper , Willi Junga , David Woodhouse Subject: Re: [PATCH] x86/io-apic: fix directed EOI when using AMd-Vi interrupt remapping On Fri, Oct 18, 2024 at 10:08:13AM +0200, Roger Pau Monne wrote: > When using AMD-VI interrupt remapping the vector field in the IO-APIC RTE= is > repurposed to contain part of the offset into the remapping table. Previ= ous to > 2ca9fbd739b8 Xen had logic so that the offset into the interrupt remapping > table would match the vector. Such logic was mandatory for end of interr= upt to > work, since the vector field (even when not containing a vector) is used = by the > IO-APIC to find for which pin the EOI must be performed. >=20 > Introduce a table to store the EOI handlers when using interrupt remappin= g, so > that the IO-APIC driver can translate pins into EOI handlers without havi= ng to > read the IO-APIC RTE entry. Note that to simplify the logic such table i= s used > unconditionally when interrupt remapping is enabled, even if strictly it = would > only be required for AMD-Vi. >=20 > Reported-by: Willi Junga > Suggested-by: David Woodhouse > Fixes: 2ca9fbd739b8 ('AMD IOMMU: allocate IRTE entries instead of using a= static mapping') > Signed-off-by: Roger Pau Monn=C3=A9 I can confirm it fixes touchpad issue on Framework 13 AMD, it works without ioapic_ack=3Dnew now, thanks! Tested-by: Marek Marczykowski-G=C3=B3recki > --- > xen/arch/x86/io_apic.c | 47 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 47 insertions(+) >=20 > diff --git a/xen/arch/x86/io_apic.c b/xen/arch/x86/io_apic.c > index e40d2f7dbd75..8856eb29d275 100644 > --- a/xen/arch/x86/io_apic.c > +++ b/xen/arch/x86/io_apic.c > @@ -71,6 +71,22 @@ static int apic_pin_2_gsi_irq(int apic, int pin); > =20 > static vmask_t *__read_mostly vector_map[MAX_IO_APICS]; > =20 > +/* > + * Store the EOI handle when using interrupt remapping. > + * > + * If using AMD-Vi interrupt remapping the IO-APIC redirection entry rem= apped > + * format repurposes the vector field to store the offset into the Inter= rupt > + * Remap table. This causes directed EOI to longer work, as the CPU vec= tor no > + * longer matches the contents of the RTE vector field. Add a translati= on > + * table so that directed EOI uses the value in the RTE vector field when > + * interrupt remapping is enabled. > + * > + * Note Intel VT-d Xen code still stores the CPU vector in the RTE vecto= r field > + * when using the remapped format, but use the translation table uniform= ly in > + * order to avoid extra logic to differentiate between VT-d and AMD-Vi. > + */ > +static unsigned int **apic_pin_eoi; > + > static void share_vector_maps(unsigned int src, unsigned int dst) > { > unsigned int pin; > @@ -273,6 +289,13 @@ void __ioapic_write_entry( > { > __io_apic_write(apic, 0x11 + 2 * pin, eu.w2); > __io_apic_write(apic, 0x10 + 2 * pin, eu.w1); > + /* > + * Might be called before apic_pin_eoi is allocated. Entry will= be > + * updated once the array is allocated and there's an EOI or wri= te > + * against the pin. > + */ > + if ( apic_pin_eoi ) > + apic_pin_eoi[apic][pin] =3D e.vector; > } > else > iommu_update_ire_from_apic(apic, pin, e.raw); > @@ -298,9 +321,17 @@ static void __io_apic_eoi(unsigned int apic, unsigne= d int vector, unsigned int p > /* Prefer the use of the EOI register if available */ > if ( ioapic_has_eoi_reg(apic) ) > { > + if ( apic_pin_eoi ) > + vector =3D apic_pin_eoi[apic][pin]; > + > /* If vector is unknown, read it from the IO-APIC */ > if ( vector =3D=3D IRQ_VECTOR_UNASSIGNED ) > + { > vector =3D __ioapic_read_entry(apic, pin, true).vector; > + if ( apic_pin_eoi ) > + /* Update cached value so further EOI don't need to fetc= h it. */ > + apic_pin_eoi[apic][pin] =3D vector; > + } > =20 > *(IO_APIC_BASE(apic)+16) =3D vector; > } > @@ -1022,7 +1053,23 @@ static void __init setup_IO_APIC_irqs(void) > =20 > apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); > =20 > + if ( iommu_intremap ) > + { > + apic_pin_eoi =3D xzalloc_array(typeof(*apic_pin_eoi), nr_ioapics= ); > + BUG_ON(!apic_pin_eoi); > + } > + > for (apic =3D 0; apic < nr_ioapics; apic++) { > + if ( iommu_intremap ) > + { > + apic_pin_eoi[apic] =3D xmalloc_array(typeof(**apic_pin_eoi), > + nr_ioapic_entries[apic]); > + BUG_ON(!apic_pin_eoi[apic]); > + > + for ( pin =3D 0; pin < nr_ioapic_entries[apic]; pin++ ) > + apic_pin_eoi[apic][pin] =3D IRQ_VECTOR_UNASSIGNED; > + } > + > for (pin =3D 0; pin < nr_ioapic_entries[apic]; pin++) { > /* > * add it to the IO-APIC irq-routing table: > --=20 > 2.46.0 >=20 >=20 --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --+AprsNGlh2aM16SR Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmcTJjoACgkQ24/THMrX 1yzaFwf8C+J4vgJ4lEOMFFSgir20FGRMxKH616PLIqdhzrMsDs+21pd9A+YbAyuL 0zf3OipSRjZhdl73klQuEuQGvrl81r5jrk0Pr6WcM29rAdufEs1zcjQVgYneRExH 2jcnGEyGih9JThhxSgq69lGir/q4MCCZdujYULKQ5QaYgKA9EVrGX4SBf0o39JM0 eFbIXObt7OeZs8CHD2ihfiPsLOF9oUd/2U6WTGIRAnAjUrzLqajNty/6TzyPtxHS SM9pjWBQIa72Z56a87Ry0vuN4OPSF5tjUAqHzxqzS9xfCLk010ZATyl7yUsiNOb3 oZrkQhNh3XjJO3ZwJXXnjqasw/52fA== =dFRW -----END PGP SIGNATURE----- --+AprsNGlh2aM16SR--