Re: [PATCH] arm64: dts: qcom: x1e80100: Route pcie5 MSIs to the GIC ITS

[Johan Hovold <johan@kernel.org>]

On Thu, Oct 24, 2024 at 05:18:14PM +0100, Marc Zyngier wrote:
> There is no reason to use the PCIe root port widget for MSIs for
> pcie5 while both pcie4 and pcie6a are enjoying the ITS.
> 
> This is specially useful when booting the kernel at EL2, as KVM
> can then configure the ITS to have MSIs directly injected in guests
> (since this machine has a GICv4.1 implementation).
> 
> Tested on a x1e001de devkit.
> 
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> Cc: Sibi Sankar <quic_sibis@quicinc.com>
> Cc: Konrad Dybcio <konradybcio@kernel.org>
> Cc: Abel Vesa <abel.vesa@linaro.org>
> Cc: Johan Hovold <johan+linaro@kernel.org>
> ---
>  arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 3441d167a5cc..48f0ebd66863 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -3281,6 +3281,8 @@ pcie5: pci@1c00000 {
>  			linux,pci-domain = <5>;
>  			num-lanes = <2>;
>  
> +			msi-map = <0x0 &gic_its 0xd0000 0x10000>;

As I just mentioned in another thread, and in the commit message of
9c4cd0aef259 ("arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe")
this was done on purpose as

	PCIe5 (and PCIe3) can currently only be used with the internal
	MSI controller due to a platform (firmware) limitation

Did you try this when booting in EL1? If so we may need to enable this
per board.

Johan