Re: [PATCH v2 1/3] clk: microchip: mpfs: support new syscon based devicetree configuration

[Leo Liang <ycliang@andestech.com>]

On Wed, Oct 23, 2024 at 11:17:52AM +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
> 
> Why get a devicetree description wrong once when you can get it wrong
> twice? The original mistake, which the driver supports was failing to
> describe the main PLL that the "cfg" and "periph" clocks parented by.
> The second mistake was describing the "cfg" and "periph" clocks a
> reg region within the clock controller, rather as two registers within
> a syscon region that also contains pinctrl, interrupt muxing controls
> and other functions.
> 
> Make up for lost time and describe these regions as they should have
> been originally, preserving support for the existing two configurations
> for the sake of existing systems with firmware-provided devicetrees.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  drivers/clk/microchip/Kconfig           |  2 +
>  drivers/clk/microchip/mpfs_clk.c        | 63 ++++++++++++++++++++-----
>  drivers/clk/microchip/mpfs_clk.h        |  5 +-
>  drivers/clk/microchip/mpfs_clk_cfg.c    | 16 +++----
>  drivers/clk/microchip/mpfs_clk_periph.c | 37 +++++++--------
>  5 files changed, 81 insertions(+), 42 deletions(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>