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[34.78.140.88]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-431bd9ca818sm25801655e9.40.2024.10.30.09.27.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Oct 2024 09:27:08 -0700 (PDT) Date: Wed, 30 Oct 2024 16:26:59 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: acpica-devel@lists.linux.dev, Hanjun Guo , iommu@lists.linux.dev, Joerg Roedel , Kevin Tian , kvm@vger.kernel.org, Len Brown , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Lorenzo Pieralisi , "Rafael J. Wysocki" , Robert Moore , Robin Murphy , Sudeep Holla , Will Deacon , Alex Williamson , Eric Auger , Jean-Philippe Brucker , Moritz Fischer , Michael Shavit , Nicolin Chen , patches@lists.linux.dev, "Rafael J. Wysocki" , Shameerali Kolothum Thodi Subject: Re: [PATCH v3 7/9] iommu/arm-smmu-v3: Expose the arm_smmu_attach interface Message-ID: References: <0-v3-e2e16cd7467f+2a6a1-smmuv3_nesting_jgg@nvidia.com> <7-v3-e2e16cd7467f+2a6a1-smmuv3_nesting_jgg@nvidia.com> Precedence: bulk X-Mailing-List: acpica-devel@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7-v3-e2e16cd7467f+2a6a1-smmuv3_nesting_jgg@nvidia.com> On Wed, Oct 09, 2024 at 01:23:13PM -0300, Jason Gunthorpe wrote: > The arm-smmuv3-iommufd.c file will need to call these functions too. > Remove statics and put them in the header file. Remove the kunit > visibility protections from arm_smmu_make_abort_ste() and > arm_smmu_make_s2_domain_ste(). > > Signed-off-by: Jason Gunthorpe Reviewed-by: Mostafa Saleh Thanks, Mostafa > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 22 ++++------------- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 27 +++++++++++++++++---- > 2 files changed, 27 insertions(+), 22 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 80847fa386fcd2..b4b03206afbf48 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -1549,7 +1549,6 @@ static void arm_smmu_write_ste(struct arm_smmu_master *master, u32 sid, > } > } > > -VISIBLE_IF_KUNIT > void arm_smmu_make_abort_ste(struct arm_smmu_ste *target) > { > memset(target, 0, sizeof(*target)); > @@ -1632,7 +1631,6 @@ void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target, > } > EXPORT_SYMBOL_IF_KUNIT(arm_smmu_make_cdtable_ste); > > -VISIBLE_IF_KUNIT > void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, > struct arm_smmu_master *master, > struct arm_smmu_domain *smmu_domain, > @@ -2505,8 +2503,8 @@ arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) > } > } > > -static void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, > - const struct arm_smmu_ste *target) > +void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, > + const struct arm_smmu_ste *target) > { > int i, j; > struct arm_smmu_device *smmu = master->smmu; > @@ -2671,16 +2669,6 @@ static void arm_smmu_remove_master_domain(struct arm_smmu_master *master, > spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); > } > > -struct arm_smmu_attach_state { > - /* Inputs */ > - struct iommu_domain *old_domain; > - struct arm_smmu_master *master; > - bool cd_needs_ats; > - ioasid_t ssid; > - /* Resulting state */ > - bool ats_enabled; > -}; > - > /* > * Start the sequence to attach a domain to a master. The sequence contains three > * steps: > @@ -2701,8 +2689,8 @@ struct arm_smmu_attach_state { > * new_domain can be a non-paging domain. In this case ATS will not be enabled, > * and invalidations won't be tracked. > */ > -static int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, > - struct iommu_domain *new_domain) > +int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, > + struct iommu_domain *new_domain) > { > struct arm_smmu_master *master = state->master; > struct arm_smmu_master_domain *master_domain; > @@ -2784,7 +2772,7 @@ static int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, > * completes synchronizing the PCI device's ATC and finishes manipulating the > * smmu_domain->devices list. > */ > -static void arm_smmu_attach_commit(struct arm_smmu_attach_state *state) > +void arm_smmu_attach_commit(struct arm_smmu_attach_state *state) > { > struct arm_smmu_master *master = state->master; > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 66261fd5bfb2d2..c9e5290e995a64 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -830,21 +830,22 @@ struct arm_smmu_entry_writer_ops { > void (*sync)(struct arm_smmu_entry_writer *writer); > }; > > +void arm_smmu_make_abort_ste(struct arm_smmu_ste *target); > +void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, > + struct arm_smmu_master *master, > + struct arm_smmu_domain *smmu_domain, > + bool ats_enabled); > + > #if IS_ENABLED(CONFIG_KUNIT) > void arm_smmu_get_ste_used(const __le64 *ent, __le64 *used_bits); > void arm_smmu_write_entry(struct arm_smmu_entry_writer *writer, __le64 *cur, > const __le64 *target); > void arm_smmu_get_cd_used(const __le64 *ent, __le64 *used_bits); > -void arm_smmu_make_abort_ste(struct arm_smmu_ste *target); > void arm_smmu_make_bypass_ste(struct arm_smmu_device *smmu, > struct arm_smmu_ste *target); > void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target, > struct arm_smmu_master *master, bool ats_enabled, > unsigned int s1dss); > -void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target, > - struct arm_smmu_master *master, > - struct arm_smmu_domain *smmu_domain, > - bool ats_enabled); > void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, > struct arm_smmu_master *master, struct mm_struct *mm, > u16 asid); > @@ -902,6 +903,22 @@ static inline bool arm_smmu_master_canwbs(struct arm_smmu_master *master) > IOMMU_FWSPEC_PCI_RC_CANWBS; > } > > +struct arm_smmu_attach_state { > + /* Inputs */ > + struct iommu_domain *old_domain; > + struct arm_smmu_master *master; > + bool cd_needs_ats; > + ioasid_t ssid; > + /* Resulting state */ > + bool ats_enabled; > +}; > + > +int arm_smmu_attach_prepare(struct arm_smmu_attach_state *state, > + struct iommu_domain *new_domain); > +void arm_smmu_attach_commit(struct arm_smmu_attach_state *state); > +void arm_smmu_install_ste_for_dev(struct arm_smmu_master *master, > + const struct arm_smmu_ste *target); > + > #ifdef CONFIG_ARM_SMMU_V3_SVA > bool arm_smmu_sva_supported(struct arm_smmu_device *smmu); > bool arm_smmu_master_sva_supported(struct arm_smmu_master *master); > -- > 2.46.2 >