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micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="o/IffRyF+aHcQMa3" Content-Disposition: inline In-Reply-To: <3663ba26192a78de2090512c912bff8afc852e5c.camel@amazon.co.uk> --o/IffRyF+aHcQMa3 Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Date: Sat, 2 Nov 2024 04:54:27 +0100 From: "marmarek@invisiblethingslab.com" To: "Woodhouse, David" Cc: "roger.pau@citrix.com" , "bp@alien8.de" , "x86@kernel.org" , "jbeulich@suse.com" , "xenproject@ymy.be" , "xen-devel@lists.xenproject.org" , "andrew.cooper3@citrix.com" Subject: Re: [PATCH] x86/io-apic: fix directed EOI when using AMd-Vi interrupt remapping On Mon, Oct 21, 2024 at 11:43:04AM +0000, Woodhouse, David wrote: > On Sat, 2024-10-19 at 05:23 +0200, Marek Marczykowski-G=C3=B3recki wrote: > > On Fri, Oct 18, 2024 at 10:08:13AM +0200, Roger Pau Monne wrote: > > > When using AMD-VI interrupt remapping the vector field in the IO-APIC= RTE is > > > repurposed to contain part of the offset into the remapping table.=C2= =A0 Previous to > > > 2ca9fbd739b8 Xen had logic so that the offset into the interrupt rema= pping > > > table would match the vector.=C2=A0 Such logic was mandatory for end = of interrupt to > > > work, since the vector field (even when not containing a vector) is u= sed by the > > > IO-APIC to find for which pin the EOI must be performed. > > >=20 > > > Introduce a table to store the EOI handlers when using interrupt rema= pping, so > > > that the IO-APIC driver can translate pins into EOI handlers without = having to > > > read the IO-APIC RTE entry.=C2=A0 Note that to simplify the logic suc= h table is used > > > unconditionally when interrupt remapping is enabled, even if strictly= it would > > > only be required for AMD-Vi. > > >=20 > > > Reported-by: Willi Junga > > > Suggested-by: David Woodhouse > > > Fixes: 2ca9fbd739b8 ('AMD IOMMU: allocate IRTE entries instead of usi= ng a static mapping') > > > Signed-off-by: Roger Pau Monn=C3=A9 > >=20 > > I can confirm it fixes touchpad issue on Framework 13 AMD, > > it works without ioapic_ack=3Dnew now, thanks! > > Tested-by: Marek Marczykowski-G=C3=B3recki >=20 > Thanks for testing. But... why did this work with the auto-EOI? That > *should* have had exactly the same problem, surely?=20 >=20 > The problem fixed by this patch is that the directed EOI used the > actual vector# and *not* the bits that the I/O APIC *thinks* are the > vector#, which are actually the IRTE index#. >=20 > But if you let the CPU do its broadcast EOI then surely *that* is going > to use the actual vector# too, and have precisely the same problem? >=20 > If you use the code prior to this patch, *without* ioapic_ack=3Dnew (i.e. > the mode that was failing), what happens if you do this: >=20 > --- a/xen/arch/x86/apic.c > +++ b/xen/arch/x86/apic.c > @@ -595,7 +595,7 @@ void setup_local_APIC(void) > /* > * Enable directed EOI > */ > - if ( directed_eoi_enabled ) > + if ( 0 && directed_eoi_enabled ) > { > value |=3D APIC_SPIV_DIRECTED_EOI; > apic_printk(APIC_VERBOSE, "Suppress EOI broadcast on CPU#%d\n", >=20 >=20 > I'm guessing that 'fixes' it too? In which case, it looks like AMD has > some undocumented hack in between its APIC and I/O APIC to let it > magically auto-EOI the correct pin somehow? So, this does _not_ fix the touchpad issue. --=20 Best Regards, Marek Marczykowski-G=C3=B3recki Invisible Things Lab --o/IffRyF+aHcQMa3 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCAAdFiEEhrpukzGPukRmQqkK24/THMrX1ywFAmclonMACgkQ24/THMrX 1ywUHAf/RZD8T7jOEZVE73t71cOtriKLLTvdVfRFC4tigM61MZiO7+Dc75k0QgVw yiVuNeA8no2+u2or7CSXvpATNO3sYugL1H9y46xKKwX2x7knhi7/F3dX4elZgJpV 7z7meePIrH8ezOWuZ0kKzgroir+fhA/m8zzmftmaQBIAyKhquCDxFpF509++yJZg fpVEFy3qYh0iojOG7QOUtmmKqWpY2oBKhEeHIleV6kQOEb1N4e3hr6ZZJgERPJ7r HGHthw6kM5IPb8Alndv2EXI/R1zxnTHBSB3rzp5rmVrkcQw5lMouKStNFCKP3Vz9 c+8+dmT6FCutZEisGAuZvuaU5LtptQ== =MFYp -----END PGP SIGNATURE----- --o/IffRyF+aHcQMa3--