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Iglesias" To: Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Cc: qemu-devel@nongnu.org, Anton Johansson , Peter Maydell , Alistair Francis , Thomas Huth , qemu-arm@nongnu.org, devel@lists.libvirt.org, =?iso-8859-1?Q?Marc-Andr=E9?= Lureau , Paolo Bonzini , Jason Wang , Richard Henderson Subject: Re: [PATCH 09/19] hw/intc/xilinx_intc: Only expect big-endian accesses Message-ID: References: <20241105130431.22564-1-philmd@linaro.org> <20241105130431.22564-10-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20241105130431.22564-10-philmd@linaro.org> User-Agent: Mutt/2.2.12 (2023-09-09) Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=edgar.iglesias@gmail.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: ZD3Pta03glj7 On Tue, Nov 05, 2024 at 02:04:21PM +0100, Philippe Mathieu-Daudé wrote: > Per the datasheet (reference added in file header, p.9) > 'Programming Model' -> 'Register Data Types and Organization': > > "The XPS INTC registers are read as big-endian data" Hi Phil, Some of these devices exist in both big and little endian versions. So far we've reused the same model by using DEVICE_NATIVE_ENDIAN. Here's the little endian version: https://docs.amd.com/v/u/en-US/ds747_axi_intc Can we have add property to select the endianess? For the Xilinx use-cases I think it may be a good idea to default it to little endian and have the big-endian machines explicitly set it. Cheers, Edgar > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/intc/xilinx_intc.c | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c > index 1762b34564e..71f743a1f14 100644 > --- a/hw/intc/xilinx_intc.c > +++ b/hw/intc/xilinx_intc.c > @@ -3,6 +3,9 @@ > * > * Copyright (c) 2009 Edgar E. Iglesias. > * > + * https://docs.amd.com/v/u/en-US/xps_intc > + * DS572: LogiCORE IP XPS Interrupt Controller (v2.01a) > + * > * Permission is hereby granted, free of charge, to any person obtaining a copy > * of this software and associated documentation files (the "Software"), to deal > * in the Software without restriction, including without limitation the rights > @@ -143,12 +146,20 @@ static void pic_write(void *opaque, hwaddr addr, > static const MemoryRegionOps pic_ops = { > .read = pic_read, > .write = pic_write, > - .endianness = DEVICE_NATIVE_ENDIAN, > + /* The XPS INTC registers are read as big-endian data. */ > + .endianness = DEVICE_BIG_ENDIAN, > .impl = { > .min_access_size = 4, > .max_access_size = 4, > }, > .valid = { > + /* > + * All XPS INTC registers are accessed through the PLB interface. > + * The base address for these registers is provided by the > + * configuration parameter, C_BASEADDR. Each register is 32 bits > + * although some bits may be unused and is accessed on a 4-byte > + * boundary offset from the base address. > + */ > .min_access_size = 4, > .max_access_size = 4, > }, > -- > 2.45.2 >