From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Mykyta Poturai <Mykyta_Poturai@epam.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Subject: Re: [XEN PATCH] xen/vpci: Fix UB in mask_write
Date: Wed, 6 Nov 2024 10:07:45 +0100 [thread overview]
Message-ID: <Zysx4ZwCUv62uTBw@macbook> (raw)
In-Reply-To: <ZyswF4grJSNcVqY_@macbook>
On Wed, Nov 06, 2024 at 10:00:07AM +0100, Roger Pau Monné wrote:
> On Wed, Nov 06, 2024 at 08:05:19AM +0000, Mykyta Poturai wrote:
> > During the construction of dmask value, it gets shifted by
> > (32 - msi->vectors) bits. If msi->vectors is 0, the result of the shift
> > becomes undefined due to shifting by a size of the type. While this
> > works fine on x86, on ARM the resulting mask becomes 0xFFFFFFFF, which
> > is incorrect.
> >
> > Fix this by adding an explicit check for msi->vectors == 0.
Wait - how can msi->vectors ever be 0? AFAICT there's no way in the
MSI logic to configure 0 vectors, there will always be at least 1 vector
enabled.
Maybe what you want, if this fix is for compliance reasons, is an
assert unreachable that msi->vectors > 0?
Thanks, Roger.
next prev parent reply other threads:[~2024-11-06 9:08 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-06 8:05 [XEN PATCH] xen/vpci: Fix UB in mask_write Mykyta Poturai
2024-11-06 9:00 ` Roger Pau Monné
2024-11-06 9:07 ` Roger Pau Monné [this message]
2024-11-06 11:31 ` Jan Beulich
2024-11-06 12:26 ` Mykyta Poturai
2024-11-06 12:42 ` Roger Pau Monné
2024-11-06 14:32 ` Mykyta Poturai
2024-11-06 14:57 ` Roger Pau Monné
2024-11-11 12:21 ` Mykyta Poturai
2024-11-12 11:26 ` Roger Pau Monné
2024-11-07 9:25 ` Jan Beulich
2024-11-07 9:36 ` Roger Pau Monné
2024-11-06 11:35 ` Jan Beulich
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