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AJvYcCUZ00krV4nnz7OlvWRVWWY7J2+WCQn3fKpabqRzsLVtV0Rl/XE64MPi4YjwhXodetNsPcM=@vger.kernel.org X-Gm-Message-State: AOJu0YxiQljhDKt3H2Ljh/NgwyVdNpsPKmPEFT+kEFdxiH9dTYOUJNCf sJHVXSanGGKyu1KX8AJLtfy3yEb8DDUF6SYOcj4BQfqyIKhC6hlBGBfVLvocSwozmRUOvL1ey2q Z2g== X-Google-Smtp-Source: AGHT+IEoAkC2h+iYko3IpB7U/mZnVavVsqzVUg9Nq3+wG63gWQho2zHdn04p22f+iDLFqDiyRdkS2WIwuDY= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:9d:3983:ac13:c240]) (user=seanjc job=sendgmr) by 2002:a17:90a:c7c4:b0:2ea:837a:b9f3 with SMTP id 98e67ed59e1d1-2eaca6bf379mr1846a91.1.1732122546420; Wed, 20 Nov 2024 09:09:06 -0800 (PST) Date: Wed, 20 Nov 2024 09:09:05 -0800 In-Reply-To: Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240801045907.4010984-1-mizhang@google.com> <20240801045907.4010984-21-mizhang@google.com> Message-ID: Subject: Re: [RFC PATCH v3 20/58] KVM: x86/pmu: Always set global enable bits in passthrough mode From: Sean Christopherson To: Dapeng Mi Cc: Mingwei Zhang , Paolo Bonzini , Xiong Zhang , Kan Liang , Zhenyu Wang , Manali Shukla , Sandipan Das , Jim Mattson , Stephane Eranian , Ian Rogers , Namhyung Kim , gce-passthrou-pmu-dev@google.com, Samantha Alt , Zhiyuan Lv , Yanfei Xu , Like Xu , Peter Zijlstra , Raghavendra Rao Ananta , kvm@vger.kernel.org, linux-perf-users@vger.kernel.org Content-Type: text/plain; charset="us-ascii" On Wed, Nov 20, 2024, Dapeng Mi wrote: > On 11/19/2024 11:37 PM, Sean Christopherson wrote: > >> --- > >> arch/x86/kvm/pmu.c | 2 +- > >> 1 file changed, 1 insertion(+), 1 deletion(-) > >> > >> diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c > >> index 5768ea2935e9..e656f72fdace 100644 > >> --- a/arch/x86/kvm/pmu.c > >> +++ b/arch/x86/kvm/pmu.c > >> @@ -787,7 +787,7 @@ void kvm_pmu_refresh(struct kvm_vcpu *vcpu) > >> * in the global controls). Emulate that behavior when refreshing the > >> * PMU so that userspace doesn't need to manually set PERF_GLOBAL_CTRL. > >> */ > >> - if (kvm_pmu_has_perf_global_ctrl(pmu) && pmu->nr_arch_gp_counters) > >> + if ((pmu->passthrough || kvm_pmu_has_perf_global_ctrl(pmu)) && pmu->nr_arch_gp_counters) > >> pmu->global_ctrl = GENMASK_ULL(pmu->nr_arch_gp_counters - 1, 0); > > This is wrong and confusing. From the guest's perspective, and therefore from > > host userspace's perspective, PERF_GLOBAL_CTRL does not exist. Therefore, the > > value that is tracked for the guest must be '0'. > > > > I see that intel_passthrough_pmu_msrs() and amd_passthrough_pmu_msrs() intercept > > accesses to PERF_GLOBAL_CTRL if "pmu->version > 1" (which, by the by, needs to be > > kvm_pmu_has_perf_global_ctrl()), so there's no weirdness with the guest being able > > to access MSRs that shouldn't exist. > > > > But KVM shouldn't stuff pmu->global_ctrl, and doing so is a symptom of another > > flaw. Unless I'm missing something, KVM stuffs pmu->global_ctrl so that the > > correct value is loaded on VM-Enter, but loading and saving PERF_GLOBAL_CTRL on > > entry/exit is unnecessary and confusing, as is loading the associated MSRs when > > restoring (loading) the guest context. > > > > For PERF_GLOBAL_CTRL on Intel, KVM needs to ensure all GP counters are enabled in > > VMCS.GUEST_IA32_PERF_GLOBAL_CTRL, but that's a "set once and forget" operation, > > not something that needs to be done on every entry and exit. Of course, loading > > and saving PERF_GLOBAL_CTRL on every entry/exit is unnecessary for other reasons, > > but that's largely orthogonal. > > > > On AMD, amd_restore_pmu_context()[*] needs to enable a maximal value for > > PERF_GLOBAL_CTRL, but I don't think there's any need to load the other MSRs, > > and the maximal value should come from the above logic, not pmu->global_ctrl. > > Sean, just double confirm, you are suggesting to do one-shot initialization > for guest PERF_GLOBAL_CTRL (VMCS.GUEST_IA32_PERF_GLOBAL_CTRL for Intel) > after vCPU resets, right? No, it would need to be written during refresh(). VMCS.GUEST_IA32_PERF_GLOBAL_CTRL is only static (because it's unreachable) if the guest does NOT have version > 1.