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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230040)(7416014)(376014)(36860700013)(82310400026)(1800799024)(30052699003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2024 20:44:58.5756 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 33a50da1-d5f1-4e28-c1af-08dd09a432b5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F6.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4234 Received-SPF: softfail client-ip=2a01:111:f403:2413::61d; envelope-from=nicolinc@nvidia.com; helo=NAM10-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.143, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org Sender: qemu-arm-bounces+alex.bennee=linaro.org@nongnu.org X-TUID: EEB6Xpo0VPF5 On Mon, Nov 18, 2024 at 06:59:53PM +0100, Eric Auger wrote: > Looking at your branch I see the following series (marked with cover-letter) .. > cover-letter: Add RMR WAR for MSI mappings (based on former RMR flat > mapping and not related to *[PATCH RFCv1 0/7] vfio: Allow userspace > to specify the address for each MSI vector > > I guess)* Yes, I think we would postpone this series, by simply putting it on top of our future shared branches while waiting for the kernel solution gets finalized to a certain degree, to make sure an MSI 2-stage mapping could still work. > cover-letter: hw/arm/virt: Add multiple nested SMMUs (Nicolin -> > Shameer) Yes > cover-letter: Add HW accelerated nesting support for arm SMMUv3 > (Nicolin) I think this will be moved to Don (or Don/Nic)? > cover-letter: Add VIOMMU infrastructure support (Nicolin) Yes. > cover-letter: intel_iommu: Enable stage-1 translation for > passthrough device (Zhenzhong) .. > cover-letter: intel_iommu: Enable stage-1 translation for emulated > device (Zhenzhong) Yes. We'll need the HWPT infrastructure patches in Intel's series and I think Intel's progress is faster so Zhenzhong should be the submitter. > *Are there any posts upstream for the rest, besides Shameer's respin? Not yet. I think the dependency should be (1) HWPT infrastructure (Zhenzhong's Intel series) (2) VIOMMU infrastructure (3) smmuv3-acc series (2-stage translation) (4) Multi vSMMU instance support (VIRT and IORT) (5) RMR > * > > > > I expect the IOMMU_HWPT_ALLOC (backend APIs) will go with Intel's > > series once their current "emulated devices" one gets merged. And > > I think I can prepare IOMMU_VIOMMU_ALLOC patches for backend APIs > > aligning with HWPT's. > Can you point us to the actual series including this IOMMU_HWPT_ALLOC > support? This would clarify which part you are going to work on next. https://github.com/yiliu1765/qemu/commits/zhenzhong/iommufd_nesting_rfcv2/ Though not planning to do so since it's unlikely the case, yet HWPT changes could go with the vSMMU series if we're running faster than Zhenzhong :) > > > > That being said, one thing I am not sure is how we should bridge > > between these backend APIs and a virtual IOMMUs (vSMMU/intel). I > > think it'd be better for you and Red Hat to provide some insight, > > if calling the backend APIs directly from a viommu module isn't a > > preferable way. > can you clarify what you call backend API in that context? > > > > We also need your comments on vSMMU module patches that are still > > roughly a draft requiring a rework at some small details I think. > > So, if your (and Don's) bandwidth allows, perhaps you could take > > over the vSMMU patches? Otherwise, we can also share the task for > > reworking. > So we have started the multi smmu instantiation review and provided > feedbacks. > Which part can we work on then? This one: cover-letter: Add HW accelerated nesting support for arm SMMUv3 i.e. (3) that I put the list above. Thanks Nicolin