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Berrange" , Yongwei Ma , Jonathan Cameron Subject: Re: [PULL 09/29] qapi/qom: Define cache enumeration and properties for machine Message-ID: References: <20241105224727.53059-1-philmd@linaro.org> <20241105224727.53059-10-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Received-SPF: pass client-ip=192.198.163.8; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -44 X-Spam_score: -4.5 X-Spam_bar: ---- X-Spam_report: (-4.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.118, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Peter, On Fri, Nov 08, 2024 at 07:10:42PM +0000, Peter Maydell wrote: > Date: Fri, 8 Nov 2024 19:10:42 +0000 > From: Peter Maydell > Subject: Re: [PULL 09/29] qapi/qom: Define cache enumeration and properties > for machine > > On Tue, 5 Nov 2024 at 22:49, Philippe Mathieu-Daudé wrote: > > > > From: Zhao Liu > > > > The x86 and ARM need to allow user to configure cache properties > > (current only topology): > > * For x86, the default cache topology model (of max/host CPU) does not > > always match the Host's real physical cache topology. Performance can > > increase when the configured virtual topology is closer to the > > physical topology than a default topology would be. > > * For ARM, QEMU can't get the cache topology information from the CPU > > registers, then user configuration is necessary. Additionally, the > > cache information is also needed for MPAM emulation (for TCG) to > > build the right PPTT. > > > > Hi; Coverity points out an issue with this change (CID 1565389): > > > diff --git a/hw/core/machine-smp.c b/hw/core/machine-smp.c > > index 5d8d7edcbd3..c6d90cd6d41 100644 > > --- a/hw/core/machine-smp.c > > +++ b/hw/core/machine-smp.c > > @@ -261,6 +261,31 @@ void machine_parse_smp_config(MachineState *ms, > > } > > } > > > > +bool machine_parse_smp_cache(MachineState *ms, > > + const SmpCachePropertiesList *caches, > > + Error **errp) > > +{ > > + const SmpCachePropertiesList *node; > > + DECLARE_BITMAP(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); > > DECLARE_BITMAP() defines the caches_bitmap bitmap, but it > does not initialize it... Yes, I missed this... > > + > > + for (node = caches; node; node = node->next) { > > + /* Prohibit users from repeating settings. */ > > + if (test_bit(node->value->cache, caches_bitmap)) { > > ...so here we are reading the variable when it is uninitialized. > > If you want to zero-initialize the bitmap you can use > bitmap_zero(caches_bitmap, CACHE_LEVEL_AND_TYPE__MAX); Thank you for your advice! I'll submit a patch to fix this! Regards, Zhao