From: "Daniel Walker (danielwa)" <danielwa@cisco.com>
To: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: "Shinichiro Kawasaki" <shinichiro.kawasaki@wdc.com>,
"Hans de Goede" <hdegoede@redhat.com>,
"Ilpo J�rvinen" <ilpo.jarvinen@linux.intel.com>,
"Klara Modin" <klarasmodin@gmail.com>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Danil Rybakov" <danilrybakov249@gmail.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"xe-linux-external(mailer list)" <xe-linux-external@cisco.com>
Subject: Re: platform/x86: p2sb: Allow p2sb_bar() calls during PCI device probe
Date: Mon, 18 Nov 2024 13:32:55 +0000 [thread overview]
Message-ID: <ZztCB5hN2NBnPgiR@goliath> (raw)
In-Reply-To: <ZztABO3TyJBekZRs@smile.fi.intel.com>
On Mon, Nov 18, 2024 at 03:24:20PM +0200, Andy Shevchenko wrote:
> On Mon, Nov 18, 2024 at 12:40:16PM +0000, Daniel Walker (danielwa) wrote:
> > On Mon, Nov 18, 2024 at 11:30:59AM +0000, Shinichiro Kawasaki wrote:
> > >
> > > Thank you. Here I quote the relevant part of the debug log.
> > >
> > > --------------------------------------------------------------------------------
> > > ...
> > > pci 0000:00:1f.0: [8086:19dc] type 00 class 0x060100 conventional PCI endpoint
> > > pci 0000:00:1f.1: [8086:19dd] type 00 class 0x058000 conventional PCI endpoint ... [A]
> > > pci 0000:00:1f.1: BAR 0 [mem 0xfd000000-0xfdffffff 64bit]
> > > pci 0000:00:1f.2: [8086:19de] type 00 class 0x058000 conventional PCI endpoint
> > > pci 0000:00:1f.2: BAR 0 [mem 0x88c00000-0x88c03fff]
> > > ...
> > > PCI: Using ACPI for IRQ routing
> > > pci 0000:00:1f.1: BAR 0 [mem 0xfd000000-0xfdffffff 64bit]: can't claim; no compatible bridge window ... [B]
> > > hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
> > > ...
> > > NET: Registered PF_XDP protocol family
> > > pci 0000:00:1f.1: BAR 0 [mem 0x280000000-0x280ffffff 64bit]: assigned ... [C]
> > > pci 0000:00:09.0: PCI bridge to [bus 01-06]
> > > ...
> > > PCI: CLS 64 bytes, default 64
> > > p2sb_cache_resources
> > > p2sb_cache_resources: P2SBC_HIDE=0 ... [D]
> > > p2sb_scan_and_cache_devfn: devfn=1f.1
> > > p2sb_scan_and_cache_devfn: 280000000-280ffffff: 140204 ... [E]
> > > PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
> > > ...
> > > --------------------------------------------------------------------------------
> > >
> > > Also, here I list my observations.
> > >
> > > [A] The P2SB device was detected with DEVFN 1f.1, and device id 8086:19dd
> > > [B] Failed to claim its resource
> > > [C] Assigned new resource
> > > [D] p2sb_cache_resource() was called after the new resource assignment.
> > > P2SBC_HIDE bit is not set.
> > > [E] The new resource was cached. IORESOURCE flags: MEM_64,SIZE_ALIGN,MEM.
> > >
> > > So it was confirmed that the p2sb_cache_resource() was called after the new
> > > resource assignment, but Hans and Andy discuss that this order is not the
> > > problem cause, probably.
> > >
> > > One thing I noticed is that p2sb_bar() call is not recorded in the log. My
> > > understanding is that all device drivers which use P2SB resource shouled call
> > > p2sb_bar(). Daniel, you noted that "a custom gpio device" disappeared. Does its
> > > device driver call p2sb_bar()?
> >
> > No calls to p2sb_bar(). It maybe an Intel GPIO device actually. 0x8086 is Intel's vendor code.
> > I suspect it's something standard on Denverton.
>
> Are you referring to LPC GPIO?
I don't know the hardware well enough to say for certain. It's whatever device 8086:19dd is.
Daniel
next prev parent reply other threads:[~2024-11-18 13:33 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-11-13 15:42 platform/x86: p2sb: Allow p2sb_bar() calls during PCI device probe Daniel Walker (danielwa)
2024-11-13 16:24 ` Hans de Goede
2024-11-13 16:33 ` Hans de Goede
2024-11-13 16:38 ` Hans de Goede
2024-11-13 17:19 ` Daniel Walker (danielwa)
2024-11-13 17:04 ` Hans de Goede
2024-11-13 17:41 ` Daniel Walker (danielwa)
2024-11-13 18:34 ` Hans de Goede
2024-11-15 11:35 ` Shinichiro Kawasaki
2024-11-15 14:57 ` Daniel Walker (danielwa)
2024-11-18 11:30 ` Shinichiro Kawasaki
2024-11-18 11:42 ` Hans de Goede
2024-11-18 12:14 ` Andy Shevchenko
2024-11-18 12:40 ` Daniel Walker (danielwa)
2024-11-18 13:24 ` Andy Shevchenko
2024-11-18 13:29 ` Hans de Goede
2024-11-18 13:52 ` Andy Shevchenko
2024-11-18 13:32 ` Daniel Walker (danielwa) [this message]
2024-11-18 13:49 ` Andy Shevchenko
2024-11-18 14:35 ` Daniel Walker (danielwa)
2024-11-18 15:55 ` Andy Shevchenko
2024-11-18 16:00 ` Hans de Goede
2024-11-18 16:08 ` Andy Shevchenko
2024-11-18 17:15 ` Daniel Walker (danielwa)
2024-11-19 2:20 ` Shinichiro Kawasaki
2024-11-19 9:37 ` Andy Shevchenko
2024-11-20 4:03 ` Shinichiro Kawasaki
2024-11-19 18:28 ` Hans de Goede
2024-11-19 20:51 ` Daniel Walker (danielwa)
2024-11-20 7:06 ` Shinichiro Kawasaki
2024-11-19 9:41 ` Andy Shevchenko
2024-11-19 14:47 ` Daniel Walker (danielwa)
2024-11-19 15:03 ` Andy Shevchenko
2024-11-13 19:17 ` Andy Shevchenko
2024-11-16 11:34 ` Hans de Goede
2024-11-18 10:05 ` Andy Shevchenko
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