From: Claudiu Beznea <claudiu.beznea@kernel.org>
To: Frank Li <Frank.li@nxp.com>,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Cc: vkoul@kernel.org, Frank.Li@kernel.org, lgirdwood@gmail.com,
broonie@kernel.org, perex@perex.cz, tiwai@suse.com,
biju.das.jz@bp.renesas.com,
prabhakar.mahadev-lad.rj@bp.renesas.com, p.zabel@pengutronix.de,
geert+renesas@glider.be, fabrizio.castro.jz@renesas.com,
kuninori.morimoto.gx@renesas.com, long.luu.ur@renesas.com,
dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-sound@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v5 12/17] dmaengine: sh: rz-dmac: Add cyclic DMA support
Date: Wed, 13 May 2026 16:38:32 +0300 [thread overview]
Message-ID: <a01a77bd-d027-410d-9f4d-0d8b51a69c82@kernel.org> (raw)
In-Reply-To: <agOjABHHVacS6ow4@lizhi-Precision-Tower-5810>
Hi, Frank,
On 5/13/26 01:00, Frank Li wrote:
> On Tue, May 12, 2026 at 03:12:13PM +0300, Claudiu Beznea wrote:
>> Add cyclic DMA support to the RZ DMAC driver. A per-channel status bit is
>> introduced to mark cyclic channels and is set during the DMA prepare
>> callback. The IRQ handler checks this status bit and calls
>> vchan_cyclic_callback() accordingly.
>>
>> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>> ---
>>
>> Changes in v5:
>> - none
>>
>> Changes in v4:
>> - drop the nxla update logic in rz_dmac_lmdesc_recycle() as this is
>> not needed for any kind of transfers
>> - drop the update of channel->status = 0 from rz_dmac_free_chan_resources()
>> and rz_dmac_terminate_all() as this was moved in patch 09/17
>>
>> Changes in v3:
>> - updated rz_dmac_lmdesc_recycle() to restore the lmdesc->nxla
>> - in rz_dmac_prepare_descs_for_cyclic() update directly the
>> desc->start_lmdesc with the descriptor pointer insted of the
>> descriptor address
>> - used rz_dmac_lmdesc_addr() to compute the descritor address
>> - set channel->status = 0 in rz_dmac_free_chan_resources()
>> - in rz_dmac_prep_dma_cyclic() check for invalid periods or buffer len
>> and limit the critical area protected by spinlock
>> - set channel->status = 0 in rz_dmac_terminate_all()
>> - updated rz_dmac_calculate_residue_bytes_in_vd() to use
>> rz_dmac_lmdesc_addr()
>> - dropped goto in rz_dmac_irq_handler_thread() as it is not needed
>> anymore; dropped also the local variable desc
>>
>> Changes in v2:
>> - none
>>
>> drivers/dma/sh/rz-dmac.c | 136 +++++++++++++++++++++++++++++++++++++--
>> 1 file changed, 130 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c
>> index 2de519b581b6..d6ad070be705 100644
>> --- a/drivers/dma/sh/rz-dmac.c
>> +++ b/drivers/dma/sh/rz-dmac.c
>> @@ -35,6 +35,7 @@
>> enum rz_dmac_prep_type {
>> RZ_DMAC_DESC_MEMCPY,
>> RZ_DMAC_DESC_SLAVE_SG,
>> + RZ_DMAC_DESC_CYCLIC,
>> };
>>
>> struct rz_lmdesc {
>> @@ -67,9 +68,11 @@ struct rz_dmac_desc {
>> /**
>> * enum rz_dmac_chan_status: RZ DMAC channel status
>> * @RZ_DMAC_CHAN_STATUS_PAUSED: Channel is paused though DMA engine callbacks
>> + * @RZ_DMAC_CHAN_STATUS_CYCLIC: Channel is cyclic
>> */
>> enum rz_dmac_chan_status {
>> RZ_DMAC_CHAN_STATUS_PAUSED,
>> + RZ_DMAC_CHAN_STATUS_CYCLIC,
>
> suggest add new field bool iscycle in rz_dmac_chan.
I would prefer as it was proposed in this patch, if all good with everybody. In
this way everything status related is packed in a single variable, struct
rz_dmac_chan::status, and only a single cleanup operation is needed when the
transactions are terminated.
>
>> };
>>
>> struct rz_dmac_chan {
>> @@ -191,6 +194,7 @@ struct rz_dmac {
>>
>> /* LINK MODE DESCRIPTOR */
>> #define HEADER_LV BIT(0)
>> +#define HEADER_WBD BIT(2)
>>
>> #define RZ_DMAC_MAX_CHAN_DESCRIPTORS 16
>> #define RZ_DMAC_MAX_CHANNELS 16
>> @@ -431,6 +435,57 @@ static void rz_dmac_prepare_descs_for_slave_sg(struct rz_dmac_chan *channel)
>> channel->chctrl = 0;
>> }
>>
> ...
>>
>> +static struct dma_async_tx_descriptor *
>> +rz_dmac_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr,
>> + size_t buf_len, size_t period_len,
>> + enum dma_transfer_direction direction,
>> + unsigned long flags)
>> +{
>> + struct rz_dmac_chan *channel = to_rz_dmac_chan(chan);
>> + struct rz_dmac_desc *desc;
>> + size_t periods;
>> +
>> + if (!is_slave_direction(direction))
>> + return NULL;
>> +
>> + if (!period_len || !buf_len)
>> + return NULL;
>> +
>> + periods = buf_len / period_len;
>> + if (!periods || periods > DMAC_NR_LMDESC)
>> + return NULL;
>> +
>> + scoped_guard(spinlock_irqsave, &channel->vc.lock) {
>> + if (channel->status & BIT(RZ_DMAC_CHAN_STATUS_CYCLIC))
>> + return NULL;
>> +
>> + desc = list_first_entry_or_null(&channel->ld_free, struct rz_dmac_desc, node);
>
> sugest use dma_pool manage desc, so ld_free can be removed.
Sure, but I would like to keep it aside from this set as it already big enough
and I haven't noticed any potential issues with it.
--
Thank you,
Claudiu
next prev parent reply other threads:[~2026-05-13 13:38 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-12 12:12 [PATCH v5 00/17] Renesas: dmaengine and ASoC fixes Claudiu Beznea
2026-05-12 12:12 ` [PATCH v5 01/17] dmaengine: sh: rz-dmac: Move interrupt request after everything is set up Claudiu Beznea
2026-05-12 20:28 ` Frank Li
2026-05-13 21:44 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 02/17] dmaengine: sh: rz-dmac: Fix incorrect NULL check on list_first_entry() Claudiu Beznea
2026-05-12 20:35 ` Frank Li
2026-05-13 13:31 ` Claudiu Beznea
2026-05-13 22:00 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 03/17] dmaengine: sh: rz-dmac: Use list_first_entry_or_null() Claudiu Beznea
2026-05-12 20:38 ` Frank Li
2026-05-13 22:18 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 04/17] dmaengine: sh: rz-dmac: Use rz_dmac_disable_hw() Claudiu Beznea
2026-05-12 20:42 ` Frank Li
2026-05-12 12:12 ` [PATCH v5 05/17] dmaengine: sh: rz-dmac: Add helper to compute the lmdesc address Claudiu Beznea
2026-05-12 20:44 ` Frank Li
2026-05-12 12:12 ` [PATCH v5 06/17] dmaengine: sh: rz-dmac: Save the start LM descriptor Claudiu Beznea
2026-05-12 20:48 ` Frank Li
2026-05-13 13:33 ` Claudiu Beznea
2026-05-13 23:52 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 07/17] dmaengine: sh: rz-dmac: Add helper to check if the channel is enabled Claudiu Beznea
2026-05-12 20:49 ` Frank Li
2026-05-13 23:59 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 08/17] dmaengine: sh: rz-dmac: Add helper to check if the channel is paused Claudiu Beznea
2026-05-12 20:57 ` Frank Li
2026-05-12 12:12 ` [PATCH v5 09/17] dmaengine: sh: rz-dmac: Use virt-dma APIs for channel descriptor processing Claudiu Beznea
2026-05-12 21:38 ` Frank Li
2026-05-13 13:34 ` Claudiu Beznea
2026-05-14 0:42 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 10/17] dmaengine: sh: rz-dmac: Refactor pause/resume code Claudiu Beznea
2026-05-12 21:43 ` Frank Li
2026-05-13 13:35 ` Claudiu Beznea
2026-05-14 0:57 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 11/17] dmaengine: sh: rz-dmac: Drop the update of channel->chctrl with CHCTRL_SETEN Claudiu Beznea
2026-05-12 21:55 ` Frank Li
2026-05-12 12:12 ` [PATCH v5 12/17] dmaengine: sh: rz-dmac: Add cyclic DMA support Claudiu Beznea
2026-05-12 22:00 ` Frank Li
2026-05-13 13:38 ` Claudiu Beznea [this message]
2026-05-14 1:43 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 13/17] dmaengine: sh: rz-dmac: Add runtime PM support Claudiu Beznea
2026-05-12 22:03 ` Frank Li
2026-05-13 13:39 ` Claudiu Beznea
2026-05-13 19:56 ` Frank Li
2026-05-14 9:20 ` Claudiu Beznea
2026-05-14 2:08 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 14/17] dmaengine: sh: rz-dmac: Add suspend to RAM support Claudiu Beznea
2026-05-14 3:04 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 15/17] ASoC: renesas: rz-ssi: Add pause support Claudiu Beznea
2026-05-14 3:54 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 16/17] ASoC: renesas: rz-ssi: Use generic PCM dmaengine APIs Claudiu Beznea
2026-05-14 4:52 ` sashiko-bot
2026-05-12 12:12 ` [PATCH v5 17/17] dmaengine: sh: rz-dmac: Set the Link End (LE) bit on the last descriptor Claudiu Beznea
2026-05-14 5:22 ` sashiko-bot
2026-05-15 8:44 ` [PATCH v5 00/17] Renesas: dmaengine and ASoC fixes John Madieu
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