From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?ISO-8859-15?Q?Ilpo_J=E4rvinen?= Subject: Re: [PATCH v2 07/12] serial: termbits: ADDRB to indicate 9th bit addressing mode Date: Mon, 4 Apr 2022 12:10:18 +0300 (EEST) Message-ID: References: <20220404082912.6885-1-ilpo.jarvinen@linux.intel.com> <20220404082912.6885-8-ilpo.jarvinen@linux.intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="8323329-1630404425-1649063432=:1675" Return-path: DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649063433; x=1680599433; h=date:from:to:cc:subject:in-reply-to:message-id: references:mime-version; bh=QqiEMALvxm0dsFsEQM+G8iM/nNOxk00l7kVM6nD9bW8=; b=ip4IK/Kz65GPYbS7B3tQML9YRAaTlXoahr+V5AZIYhkWW9/9bgZOzq4p 40j04R1qFEMdckxTwxoLJZ8U2itWze56LHrq2BDWjUSnyXjxnc+1ke9w0 DEjmKIhvMXKz3q/2ZoTfVjpvXfnYJ52JKocJoYuna+mqAt89zPKfolORo s5eImJyff5Oga1xNg0Q8mxAnDvOEoDUeEpt0DLejpFbL5ZbmBW9cVTH4r Fhwstbx3Hahw6CexOHXvj53Vb+iKCpH8M30wv0YsmuFhXrwZKWTMaBbeP awgM103wDaRf2/7G9PyTRCYoG+ZXYA0+LmQAtBT+tgVIBO4Y85p+GcR5j w==; In-Reply-To: List-ID: To: Arnd Bergmann Cc: "open list:SERIAL DRIVERS" , Greg KH , Jiri Slaby , Lukas Wunner , Andy Shevchenko , Johan Hovold , Heiko Stuebner , giulio.benetti-W14uJ/fiAyBY2hyreNRi6g@public.gmane.org, Heikki Krogerus , =?ISO-8859-15?Q?Uwe_Kleine-K=F6nig?= , Linux API , Ivan Kokshaysky , Matt Turner , alpha , Thomas Bogendoerfer , "open list:BROADCOM NVRAM DRIVER" , "James E.J. Bottomley" This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-1630404425-1649063432=:1675 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Mon, 4 Apr 2022, Arnd Bergmann wrote: > On Mon, Apr 4, 2022 at 10:29 AM Ilpo Järvinen > wrote: > > > > > #define CLOCAL 00100000 > > +#define ADDRB 010000000 /* address bit */ > > #define CMSPAR 010000000000 /* mark or space (stick) parity */ > > #define CRTSCTS 020000000000 /* flow control */ > > > > diff --git a/arch/mips/include/uapi/asm/termbits.h b/arch/mips/include/uapi/asm/termbits.h > > index dfeffba729b7..e7ea31cfec78 100644 > > --- a/arch/mips/include/uapi/asm/termbits.h > > +++ b/arch/mips/include/uapi/asm/termbits.h > > @@ -181,6 +181,7 @@ struct ktermios { > > #define B3000000 0010015 > > #define B3500000 0010016 > > #define B4000000 0010017 > > +#define ADDRB 0020000 /* address bit */ > > #define CIBAUD 002003600000 /* input baud rate */ > > #define CMSPAR 010000000000 /* mark or space (stick) parity */ > > #define CRTSCTS 020000000000 /* flow control */ > > It looks like the top bits are used the same way on all architectures > already, while the bottom bits of the flag differ. Could you pick > the next free bit from the top to use the same value 04000000000 > everywhere? 04000000000 isn't the top of the use: diff --git a/arch/alpha/include/uapi/asm/termbits.h b/arch/alpha/include/uapi/asm/termbits.h index 4575ba34a0ea..285169c794ec 100644 --- a/arch/alpha/include/uapi/asm/termbits.h +++ b/arch/alpha/include/uapi/asm/termbits.h @@ -178,10 +178,11 @@ struct ktermios { #define PARENB 00010000 #define PARODD 00020000 #define HUPCL 00040000 #define CLOCAL 00100000 +#define ADDRB 010000000 /* address bit */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ #define CIBAUD 07600000 #define IBSHIFT 16 diff --git a/arch/sparc/include/uapi/asm/termbits.h b/arch/sparc/include/uapi/asm/termbits.h index ce5ad5d0f105..4ad60c4acf65 100644 --- a/arch/sparc/include/uapi/asm/termbits.h +++ b/arch/sparc/include/uapi/asm/termbits.h @@ -198,10 +198,11 @@ struct ktermios { adjust CBAUD constant and drivers accordingly. #define B4000000 0x00001013 */ +#define ADDRB 0x00002000 /* address bit */ #define CIBAUD 0x100f0000 /* input baud rate (not used) */ #define CMSPAR 0x40000000 /* mark or space (stick) parity */ #define CRTSCTS 0x80000000 /* flow control */ Somehow I managed to convince myself earlier there isn't a bit available that would be consistent across archs but now that I recheck the 04000000000 bit (0x20000000) you propose, it seems to be that nothing is using it. It's not suprising I didn't get the magnitude of those long octal numbers right. ...They are such a pain to interpret correctly. -- i. --8323329-1630404425-1649063432=:1675-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51AB3C4332F for ; Mon, 4 Apr 2022 09:10:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349592AbiDDJMa (ORCPT ); Mon, 4 Apr 2022 05:12:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240647AbiDDJM3 (ORCPT ); Mon, 4 Apr 2022 05:12:29 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FF202F382; Mon, 4 Apr 2022 02:10:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649063433; x=1680599433; h=date:from:to:cc:subject:in-reply-to:message-id: references:mime-version; bh=QqiEMALvxm0dsFsEQM+G8iM/nNOxk00l7kVM6nD9bW8=; b=ip4IK/Kz65GPYbS7B3tQML9YRAaTlXoahr+V5AZIYhkWW9/9bgZOzq4p 40j04R1qFEMdckxTwxoLJZ8U2itWze56LHrq2BDWjUSnyXjxnc+1ke9w0 DEjmKIhvMXKz3q/2ZoTfVjpvXfnYJ52JKocJoYuna+mqAt89zPKfolORo s5eImJyff5Oga1xNg0Q8mxAnDvOEoDUeEpt0DLejpFbL5ZbmBW9cVTH4r Fhwstbx3Hahw6CexOHXvj53Vb+iKCpH8M30wv0YsmuFhXrwZKWTMaBbeP awgM103wDaRf2/7G9PyTRCYoG+ZXYA0+LmQAtBT+tgVIBO4Y85p+GcR5j w==; X-IronPort-AV: E=McAfee;i="6200,9189,10306"; a="323646112" X-IronPort-AV: E=Sophos;i="5.90,233,1643702400"; d="scan'208";a="323646112" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2022 02:10:32 -0700 X-IronPort-AV: E=Sophos;i="5.90,233,1643702400"; d="scan'208";a="569307128" Received: from rhamza-mobl.ger.corp.intel.com ([10.251.211.126]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2022 02:10:25 -0700 Date: Mon, 4 Apr 2022 12:10:18 +0300 (EEST) From: =?ISO-8859-15?Q?Ilpo_J=E4rvinen?= To: Arnd Bergmann cc: "open list:SERIAL DRIVERS" , Greg KH , Jiri Slaby , Lukas Wunner , Andy Shevchenko , Johan Hovold , Heiko Stuebner , giulio.benetti@micronovasrl.com, Heikki Krogerus , =?ISO-8859-15?Q?Uwe_Kleine-K=F6nig?= , Linux API , Ivan Kokshaysky , Matt Turner , alpha , Thomas Bogendoerfer , "open list:BROADCOM NVRAM DRIVER" , "James E.J. Bottomley" , Helge Deller , Parisc List , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , linuxppc-dev , "David S. Miller" , sparclinux , linux-arch , USB list Subject: Re: [PATCH v2 07/12] serial: termbits: ADDRB to indicate 9th bit addressing mode In-Reply-To: Message-ID: References: <20220404082912.6885-1-ilpo.jarvinen@linux.intel.com> <20220404082912.6885-8-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8323329-1630404425-1649063432=:1675" Precedence: bulk List-ID: X-Mailing-List: linux-api@vger.kernel.org This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-1630404425-1649063432=:1675 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT On Mon, 4 Apr 2022, Arnd Bergmann wrote: > On Mon, Apr 4, 2022 at 10:29 AM Ilpo Järvinen > wrote: > > > > > #define CLOCAL 00100000 > > +#define ADDRB 010000000 /* address bit */ > > #define CMSPAR 010000000000 /* mark or space (stick) parity */ > > #define CRTSCTS 020000000000 /* flow control */ > > > > diff --git a/arch/mips/include/uapi/asm/termbits.h b/arch/mips/include/uapi/asm/termbits.h > > index dfeffba729b7..e7ea31cfec78 100644 > > --- a/arch/mips/include/uapi/asm/termbits.h > > +++ b/arch/mips/include/uapi/asm/termbits.h > > @@ -181,6 +181,7 @@ struct ktermios { > > #define B3000000 0010015 > > #define B3500000 0010016 > > #define B4000000 0010017 > > +#define ADDRB 0020000 /* address bit */ > > #define CIBAUD 002003600000 /* input baud rate */ > > #define CMSPAR 010000000000 /* mark or space (stick) parity */ > > #define CRTSCTS 020000000000 /* flow control */ > > It looks like the top bits are used the same way on all architectures > already, while the bottom bits of the flag differ. Could you pick > the next free bit from the top to use the same value 04000000000 > everywhere? 04000000000 isn't the top of the use: diff --git a/arch/alpha/include/uapi/asm/termbits.h b/arch/alpha/include/uapi/asm/termbits.h index 4575ba34a0ea..285169c794ec 100644 --- a/arch/alpha/include/uapi/asm/termbits.h +++ b/arch/alpha/include/uapi/asm/termbits.h @@ -178,10 +178,11 @@ struct ktermios { #define PARENB 00010000 #define PARODD 00020000 #define HUPCL 00040000 #define CLOCAL 00100000 +#define ADDRB 010000000 /* address bit */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ #define CIBAUD 07600000 #define IBSHIFT 16 diff --git a/arch/sparc/include/uapi/asm/termbits.h b/arch/sparc/include/uapi/asm/termbits.h index ce5ad5d0f105..4ad60c4acf65 100644 --- a/arch/sparc/include/uapi/asm/termbits.h +++ b/arch/sparc/include/uapi/asm/termbits.h @@ -198,10 +198,11 @@ struct ktermios { adjust CBAUD constant and drivers accordingly. #define B4000000 0x00001013 */ +#define ADDRB 0x00002000 /* address bit */ #define CIBAUD 0x100f0000 /* input baud rate (not used) */ #define CMSPAR 0x40000000 /* mark or space (stick) parity */ #define CRTSCTS 0x80000000 /* flow control */ Somehow I managed to convince myself earlier there isn't a bit available that would be consistent across archs but now that I recheck the 04000000000 bit (0x20000000) you propose, it seems to be that nothing is using it. It's not suprising I didn't get the magnitude of those long octal numbers right. ...They are such a pain to interpret correctly. -- i. --8323329-1630404425-1649063432=:1675-- From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1244BC433EF for ; Mon, 4 Apr 2022 09:12:27 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4KX4mT3YjLz3bcc for ; Mon, 4 Apr 2022 19:12:25 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=EEMOK8nA; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=none (no SPF record) smtp.mailfrom=linux.intel.com (client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=ilpo.jarvinen@linux.intel.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=EEMOK8nA; dkim-atps=neutral Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4KX4lk6hSlz2xnK for ; Mon, 4 Apr 2022 19:11:45 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1649063507; x=1680599507; h=date:from:to:cc:subject:in-reply-to:message-id: references:mime-version; bh=QqiEMALvxm0dsFsEQM+G8iM/nNOxk00l7kVM6nD9bW8=; b=EEMOK8nAeyZmjN9IQglJUDi4qa7SrHiMHAzaa/r9sJI7COOa6v/2gdmN a/BpxjcFSFBHIlVrWqU8sBm/AX+hZ9RvDwCUNDmdhY2BYlSKerPOCSeeJ eoZOuAKEwnVaTSxFDCWNqk6sKQ/s6UgQhg0wcHfwLvaJjAzpCk3icmQ94 0ko0SoIyHUJ//UJTHNaQ9kdhOJBsjGmEv+S/+EnJJtOXSFEy+t9AotJUD 4PfnXcKZ5XR9jVym9woSsFujdgVfq/dnW8c1pDGFy8rallbU+ZZbdoxmk qv+Ze9wud37yJkcA4ZxZ9e3+c1trwNWxbx6/Tv8I998kriQTvADe5yhkw A==; X-IronPort-AV: E=McAfee;i="6200,9189,10306"; a="258053076" X-IronPort-AV: E=Sophos;i="5.90,233,1643702400"; d="scan'208";a="258053076" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2022 02:10:33 -0700 X-IronPort-AV: E=Sophos;i="5.90,233,1643702400"; d="scan'208";a="569307128" Received: from rhamza-mobl.ger.corp.intel.com ([10.251.211.126]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Apr 2022 02:10:25 -0700 Date: Mon, 4 Apr 2022 12:10:18 +0300 (EEST) From: =?ISO-8859-15?Q?Ilpo_J=E4rvinen?= To: Arnd Bergmann Subject: Re: [PATCH v2 07/12] serial: termbits: ADDRB to indicate 9th bit addressing mode In-Reply-To: Message-ID: References: <20220404082912.6885-1-ilpo.jarvinen@linux.intel.com> <20220404082912.6885-8-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8323329-1630404425-1649063432=:1675" X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Heikki Krogerus , Heiko Stuebner , "James E.J. Bottomley" , Paul Mackerras , sparclinux , Linux API , Jiri Slaby , linux-arch , Helge Deller , "open list:SERIAL DRIVERS" , =?ISO-8859-15?Q?Uwe_Kleine-K=F6nig?= , Matt Turner , Johan Hovold , Ivan Kokshaysky , Andy Shevchenko , Thomas Bogendoerfer , Parisc List , Greg KH , USB list , "open list:BROADCOM NVRAM DRIVER" , "David S. Miller" , Lukas Wunner , alpha , linuxppc-dev , giulio.benetti@micronovasrl.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --8323329-1630404425-1649063432=:1675 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT On Mon, 4 Apr 2022, Arnd Bergmann wrote: > On Mon, Apr 4, 2022 at 10:29 AM Ilpo Järvinen > wrote: > > > > > #define CLOCAL 00100000 > > +#define ADDRB 010000000 /* address bit */ > > #define CMSPAR 010000000000 /* mark or space (stick) parity */ > > #define CRTSCTS 020000000000 /* flow control */ > > > > diff --git a/arch/mips/include/uapi/asm/termbits.h b/arch/mips/include/uapi/asm/termbits.h > > index dfeffba729b7..e7ea31cfec78 100644 > > --- a/arch/mips/include/uapi/asm/termbits.h > > +++ b/arch/mips/include/uapi/asm/termbits.h > > @@ -181,6 +181,7 @@ struct ktermios { > > #define B3000000 0010015 > > #define B3500000 0010016 > > #define B4000000 0010017 > > +#define ADDRB 0020000 /* address bit */ > > #define CIBAUD 002003600000 /* input baud rate */ > > #define CMSPAR 010000000000 /* mark or space (stick) parity */ > > #define CRTSCTS 020000000000 /* flow control */ > > It looks like the top bits are used the same way on all architectures > already, while the bottom bits of the flag differ. Could you pick > the next free bit from the top to use the same value 04000000000 > everywhere? 04000000000 isn't the top of the use: diff --git a/arch/alpha/include/uapi/asm/termbits.h b/arch/alpha/include/uapi/asm/termbits.h index 4575ba34a0ea..285169c794ec 100644 --- a/arch/alpha/include/uapi/asm/termbits.h +++ b/arch/alpha/include/uapi/asm/termbits.h @@ -178,10 +178,11 @@ struct ktermios { #define PARENB 00010000 #define PARODD 00020000 #define HUPCL 00040000 #define CLOCAL 00100000 +#define ADDRB 010000000 /* address bit */ #define CMSPAR 010000000000 /* mark or space (stick) parity */ #define CRTSCTS 020000000000 /* flow control */ #define CIBAUD 07600000 #define IBSHIFT 16 diff --git a/arch/sparc/include/uapi/asm/termbits.h b/arch/sparc/include/uapi/asm/termbits.h index ce5ad5d0f105..4ad60c4acf65 100644 --- a/arch/sparc/include/uapi/asm/termbits.h +++ b/arch/sparc/include/uapi/asm/termbits.h @@ -198,10 +198,11 @@ struct ktermios { adjust CBAUD constant and drivers accordingly. #define B4000000 0x00001013 */ +#define ADDRB 0x00002000 /* address bit */ #define CIBAUD 0x100f0000 /* input baud rate (not used) */ #define CMSPAR 0x40000000 /* mark or space (stick) parity */ #define CRTSCTS 0x80000000 /* flow control */ Somehow I managed to convince myself earlier there isn't a bit available that would be consistent across archs but now that I recheck the 04000000000 bit (0x20000000) you propose, it seems to be that nothing is using it. It's not suprising I didn't get the magnitude of those long octal numbers right. ...They are such a pain to interpret correctly. -- i. --8323329-1630404425-1649063432=:1675--