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Smith" , Ross Philipson , Jan Beulich , =?UTF-8?Q?Roger_Pau_Monn=C3=A9?= , Lukasz Hawrylko , =?UTF-8?Q?Mateusz_M=C3=B3wka?= , trenchboot-devel@googlegroups.com References: Content-Language: en-GB From: Andrew Cooper Autocrypt: addr=andrew.cooper3@citrix.com; keydata= xsFNBFLhNn8BEADVhE+Hb8i0GV6mihnnr/uiQQdPF8kUoFzCOPXkf7jQ5sLYeJa0cQi6Penp VtiFYznTairnVsN5J+ujSTIb+OlMSJUWV4opS7WVNnxHbFTPYZVQ3erv7NKc2iVizCRZ2Kxn srM1oPXWRic8BIAdYOKOloF2300SL/bIpeD+x7h3w9B/qez7nOin5NzkxgFoaUeIal12pXSR Q354FKFoy6Vh96gc4VRqte3jw8mPuJQpfws+Pb+swvSf/i1q1+1I4jsRQQh2m6OTADHIqg2E ofTYAEh7R5HfPx0EXoEDMdRjOeKn8+vvkAwhviWXTHlG3R1QkbE5M/oywnZ83udJmi+lxjJ5 YhQ5IzomvJ16H0Bq+TLyVLO/VRksp1VR9HxCzItLNCS8PdpYYz5TC204ViycobYU65WMpzWe LFAGn8jSS25XIpqv0Y9k87dLbctKKA14Ifw2kq5OIVu2FuX+3i446JOa2vpCI9GcjCzi3oHV e00bzYiHMIl0FICrNJU0Kjho8pdo0m2uxkn6SYEpogAy9pnatUlO+erL4LqFUO7GXSdBRbw5 gNt25XTLdSFuZtMxkY3tq8MFss5QnjhehCVPEpE6y9ZjI4XB8ad1G4oBHVGK5LMsvg22PfMJ ISWFSHoF/B5+lHkCKWkFxZ0gZn33ju5n6/FOdEx4B8cMJt+cWwARAQABzSlBbmRyZXcgQ29v cGVyIDxhbmRyZXcuY29vcGVyM0BjaXRyaXguY29tPsLBegQTAQgAJAIbAwULCQgHAwUVCgkI CwUWAgMBAAIeAQIXgAUCWKD95wIZAQAKCRBlw/kGpdefoHbdD/9AIoR3k6fKl+RFiFpyAhvO 59ttDFI7nIAnlYngev2XUR3acFElJATHSDO0ju+hqWqAb8kVijXLops0gOfqt3VPZq9cuHlh IMDquatGLzAadfFx2eQYIYT+FYuMoPZy/aTUazmJIDVxP7L383grjIkn+7tAv+qeDfE+txL4 SAm1UHNvmdfgL2/lcmL3xRh7sub3nJilM93RWX1Pe5LBSDXO45uzCGEdst6uSlzYR/MEr+5Z JQQ32JV64zwvf/aKaagSQSQMYNX9JFgfZ3TKWC1KJQbX5ssoX/5hNLqxMcZV3TN7kU8I3kjK mPec9+1nECOjjJSO/h4P0sBZyIUGfguwzhEeGf4sMCuSEM4xjCnwiBwftR17sr0spYcOpqET ZGcAmyYcNjy6CYadNCnfR40vhhWuCfNCBzWnUW0lFoo12wb0YnzoOLjvfD6OL3JjIUJNOmJy RCsJ5IA/Iz33RhSVRmROu+TztwuThClw63g7+hoyewv7BemKyuU6FTVhjjW+XUWmS/FzknSi dAG+insr0746cTPpSkGl3KAXeWDGJzve7/SBBfyznWCMGaf8E2P1oOdIZRxHgWj0zNr1+ooF /PzgLPiCI4OMUttTlEKChgbUTQ+5o0P080JojqfXwbPAyumbaYcQNiH1/xYbJdOFSiBv9rpt TQTBLzDKXok86M7BTQRS4TZ/ARAAkgqudHsp+hd82UVkvgnlqZjzz2vyrYfz7bkPtXaGb9H4 Rfo7mQsEQavEBdWWjbga6eMnDqtu+FC+qeTGYebToxEyp2lKDSoAsvt8w82tIlP/EbmRbDVn 7bhjBlfRcFjVYw8uVDPptT0TV47vpoCVkTwcyb6OltJrvg/QzV9f07DJswuda1JH3/qvYu0p vjPnYvCq4NsqY2XSdAJ02HrdYPFtNyPEntu1n1KK+gJrstjtw7KsZ4ygXYrsm/oCBiVW/OgU g/XIlGErkrxe4vQvJyVwg6YH653YTX5hLLUEL1NS4TCo47RP+wi6y+TnuAL36UtK/uFyEuPy wwrDVcC4cIFhYSfsO0BumEI65yu7a8aHbGfq2lW251UcoU48Z27ZUUZd2Dr6O/n8poQHbaTd 6bJJSjzGGHZVbRP9UQ3lkmkmc0+XCHmj5WhwNNYjgbbmML7y0fsJT5RgvefAIFfHBg7fTY/i kBEimoUsTEQz+N4hbKwo1hULfVxDJStE4sbPhjbsPCrlXf6W9CxSyQ0qmZ2bXsLQYRj2xqd1 bpA+1o1j2N4/au1R/uSiUFjewJdT/LX1EklKDcQwpk06Af/N7VZtSfEJeRV04unbsKVXWZAk uAJyDDKN99ziC0Wz5kcPyVD1HNf8bgaqGDzrv3TfYjwqayRFcMf7xJaL9xXedMcAEQEAAcLB XwQYAQgACQUCUuE2fwIbDAAKCRBlw/kGpdefoG4XEACD1Qf/er8EA7g23HMxYWd3FXHThrVQ HgiGdk5Yh632vjOm9L4sd/GCEACVQKjsu98e8o3ysitFlznEns5EAAXEbITrgKWXDDUWGYxd pnjj2u+GkVdsOAGk0kxczX6s+VRBhpbBI2PWnOsRJgU2n10PZ3mZD4Xu9kU2IXYmuW+e5KCA vTArRUdCrAtIa1k01sPipPPw6dfxx2e5asy21YOytzxuWFfJTGnVxZZSCyLUO83sh6OZhJkk b9rxL9wPmpN/t2IPaEKoAc0FTQZS36wAMOXkBh24PQ9gaLJvfPKpNzGD8XWR5HHF0NLIJhgg 4ZlEXQ2fVp3XrtocHqhu4UZR4koCijgB8sB7Tb0GCpwK+C4UePdFLfhKyRdSXuvY3AHJd4CP 4JzW0Bzq/WXY3XMOzUTYApGQpnUpdOmuQSfpV9MQO+/jo7r6yPbxT7CwRS5dcQPzUiuHLK9i nvjREdh84qycnx0/6dDroYhp0DFv4udxuAvt1h4wGwTPRQZerSm4xaYegEFusyhbZrI0U9tJ B8WrhBLXDiYlyJT6zOV2yZFuW47VrLsjYnHwn27hmxTC/7tvG3euCklmkn9Sl9IAKFu29RSo d5bD8kMSCYsTqtTfT6W4A3qHGvIDta3ptLYpIAOD2sY3GYq2nf3Bbzx81wZK14JdDDHUX2Rs 6+ahAA== In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 13/05/2025 6:05 pm, Sergii Dmytruk wrote: > diff --git a/xen/arch/x86/include/asm/intel-txt.h b/xen/arch/x86/include/asm/intel-txt.h > new file mode 100644 > index 0000000000..07be43f557 > --- /dev/null > +++ b/xen/arch/x86/include/asm/intel-txt.h > @@ -0,0 +1,277 @@ > +/* SPDX-License-Identifier: GPL-2.0-or-later */ > + Please have at least a one-liner introduction to what TXT is.  Is there a stable URL for the TXT spec?  (I can't spot an obvious one, googling around) > +#ifndef ASM__X86__INTEL_TXT_H > +#define ASM__X86__INTEL_TXT_H I realise this is what the documentation currently says, but we're just in the process of finalising some changes.  Please make this X86_INTEL_TXT_H. > + > +/* > + * TXT configuration registers (offsets from TXT_{PUB, PRIV}_CONFIG_REGS_BASE) > + */ > +#define TXT_PUB_CONFIG_REGS_BASE 0xfed30000U > +#define TXT_PRIV_CONFIG_REGS_BASE 0xfed20000U > + > +/* > + * The same set of registers is exposed twice (with different permissions) and > + * they are allocated continuously with page alignment. > + */ > +#define NR_TXT_CONFIG_SIZE \ > + (TXT_PUB_CONFIG_REGS_BASE - TXT_PRIV_CONFIG_REGS_BASE) Commit message needs to note that you're swapping NR_TXT_CONFIG_PAGES for NR_TXT_CONFIG_SIZE, hence the change in logic in tboot_protect_mem_regions(). > +#ifndef __ASSEMBLY__ > + > +/* Need to differentiate between pre- and post paging enabled. */ > +#ifdef __EARLY_SLAUNCH__ > +#include > +#define _txt(x) _p(x) > +#else > +#include > +#include // __va() > +#define _txt(x) __va(x) > +#endif I have to admit that I'm rather suspicious of this, but I'm going to have to wait to see later patches before making a suggestion.  (I highly suspect we'll want a fixmap entry). > + > +/* > + * Always use private space as some of registers are either read-only or not > + * present in public space. > + */ > +static inline uint64_t read_txt_reg(int reg_no) unsigned int reg I'd be tempted to name it simply txt_read().  I don't think the extra "_reg" is a helpful suffix, and it makes the APIs consistent with txt_reset().  But I expect others may have opinions here. > +{ > + volatile uint64_t *reg = _txt(TXT_PRIV_CONFIG_REGS_BASE + reg_no); > + return *reg; > +} > + > +static inline void write_txt_reg(int reg_no, uint64_t val) > +{ > + volatile uint64_t *reg = _txt(TXT_PRIV_CONFIG_REGS_BASE + reg_no); > + *reg = val; > + /* This serves as TXT register barrier */ > + (void)read_txt_reg(TXTCR_ESTS); What is this barrier for? It's not for anything in the CPU side of things, because UC accesses are strictly ordered. I presume it's for LPC bus ordering then, but making every write be a write/read pair seems very expensive. > +} > + > +static inline void txt_reset(uint32_t error) > +{ > + write_txt_reg(TXTCR_ERRORCODE, error); > + write_txt_reg(TXTCR_CMD_NO_SECRETS, 1); > + write_txt_reg(TXTCR_CMD_UNLOCK_MEM_CONFIG, 1); > + write_txt_reg(TXTCR_CMD_RESET, 1); > + while (1); for ( ;; )     cpu_relax(); please. Will the write to CMD_RESET try to initiate a platform reset, or will we just hang here forever? > +/* > + * Functions to extract data from the Intel TXT Heap Memory. The layout > + * of the heap is as follows: > + * +------------------------------------+ > + * | Size of Bios Data table (uint64_t) | > + * +------------------------------------+ > + * | Bios Data table | > + * +------------------------------------+ > + * | Size of OS MLE table (uint64_t) | > + * +------------------------------------+ > + * | OS MLE table | > + * +-------------------------------- + > + * | Size of OS SINIT table (uint64_t) | > + * +------------------------------------+ > + * | OS SINIT table | > + * +------------------------------------+ > + * | Size of SINIT MLE table (uint64_t) | > + * +------------------------------------+ > + * | SINIT MLE table | > + * +------------------------------------+ > + * > + * NOTE: the table size fields include the 8 byte size field itself. > + */ > +static inline uint64_t txt_bios_data_size(void *heap) > +{ > + return *((uint64_t *)heap) - sizeof(uint64_t); > +} This is quite horrible, but I presume this is as specified by TXT? To confirm, it's a tightly packed data structure where each of the 4 blobs is variable size?  Are there any alignment requirements on the table sizes?  I suspect not, given the __packed attributes. > diff --git a/xen/arch/x86/tboot.c b/xen/arch/x86/tboot.c > index d5db60d335..8a573d8c79 100644 > --- a/xen/arch/x86/tboot.c > +++ b/xen/arch/x86/tboot.c > @@ -15,6 +15,7 @@ > #include > #include > #include > +#include > > #include I'll send a prep patch to fix tboot.c, but we're trying to keep includes sorted (for sanity of backports). ~Andrew