From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C9E1C433FE for ; Thu, 19 May 2022 06:53:59 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4L3gYx6NmZz30G6 for ; Thu, 19 May 2022 16:53:57 +1000 (AEST) Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=huawei.com (client-ip=45.249.212.188; helo=szxga02-in.huawei.com; envelope-from=tongtiangen@huawei.com; receiver=) Received: from szxga02-in.huawei.com (szxga02-in.huawei.com [45.249.212.188]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4L3gYJ3WQ2z307g for ; Thu, 19 May 2022 16:53:24 +1000 (AEST) Received: from kwepemi500012.china.huawei.com (unknown [172.30.72.56]) by szxga02-in.huawei.com (SkyGuard) with ESMTP id 4L3gXB3kSbzhYlT; Thu, 19 May 2022 14:52:26 +0800 (CST) Received: from kwepemm600017.china.huawei.com (7.193.23.234) by kwepemi500012.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 19 May 2022 14:53:17 +0800 Received: from [10.174.179.234] (10.174.179.234) by kwepemm600017.china.huawei.com (7.193.23.234) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Thu, 19 May 2022 14:53:15 +0800 Message-ID: Date: Thu, 19 May 2022 14:53:14 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH -next v4 4/7] arm64: add copy_{to, from}_user to machine check safe To: Mark Rutland References: <20220420030418.3189040-1-tongtiangen@huawei.com> <20220420030418.3189040-5-tongtiangen@huawei.com> From: Tong Tiangen In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.174.179.234] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemm600017.china.huawei.com (7.193.23.234) X-CFilter-Loop: Reflected X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kefeng Wang , Dave Hansen , linux-mm@kvack.org, Paul Mackerras , Guohanjun , Will Deacon , "H . Peter Anvin" , x86@kernel.org, Ingo Molnar , Catalin Marinas , Xie XiuQi , Borislav Petkov , Alexander Viro , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Robin Murphy , linux-kernel@vger.kernel.org, James Morse , Andrew Morton , linuxppc-dev@lists.ozlabs.org Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" 在 2022/5/13 23:31, Mark Rutland 写道: > On Wed, Apr 20, 2022 at 03:04:15AM +0000, Tong Tiangen wrote: >> Add copy_{to, from}_user() to machine check safe. >> >> If copy fail due to hardware memory error, only the relevant processes are >> affected, so killing the user process and isolate the user page with >> hardware memory errors is a more reasonable choice than kernel panic. >> >> Add new extable type EX_TYPE_UACCESS_MC which can be used for uaccess that >> can be recovered from hardware memory errors. > > I don't understand why we need this. > > If we apply EX_TYPE_UACCESS consistently to *all* user accesses, and > *only* to user accesses, that would *always* indicate that we can > recover, and that seems much simpler to deal with. > > Today we use EX_TYPE_UACCESS_ERR_ZERO for kernel accesses in a couple of > cases, which we should clean up, and we user EX_TYPE_FIXUP for a couple > of user accesses, but those could easily be converted over. > >> The x16 register is used to save the fixup type in copy_xxx_user which >> used extable type EX_TYPE_UACCESS_MC. This is dicussed on patch patch 3/7. > > Why x16? > > How is this intended to be consumed, and why is that behaviour different > from any *other* fault? > > Mark. This is to distinguish EX_TYPE_FIXUP, if this exception is triggered, in fixup processing, it is needed to copy by byte, but if exception is triggered by machine check, the data does not need to be copied again. So we need one place to store exception type, Therefore, X16 that is not currently used in copy_from/to_user is selected. Maybe better to use exception_table_entry->data to pass the register that needs to be set? Thanks, Tong. > >> Signed-off-by: Tong Tiangen >> --- >> arch/arm64/include/asm/asm-extable.h | 14 ++++++++++++++ >> arch/arm64/include/asm/asm-uaccess.h | 15 ++++++++++----- >> arch/arm64/lib/copy_from_user.S | 18 +++++++++++------- >> arch/arm64/lib/copy_to_user.S | 18 +++++++++++------- >> arch/arm64/mm/extable.c | 18 ++++++++++++++---- >> 5 files changed, 60 insertions(+), 23 deletions(-) >> >> diff --git a/arch/arm64/include/asm/asm-extable.h b/arch/arm64/include/asm/asm-extable.h >> index c39f2437e08e..75b2c00e9523 100644 >> --- a/arch/arm64/include/asm/asm-extable.h >> +++ b/arch/arm64/include/asm/asm-extable.h >> @@ -2,12 +2,18 @@ >> #ifndef __ASM_ASM_EXTABLE_H >> #define __ASM_ASM_EXTABLE_H >> >> +#define FIXUP_TYPE_NORMAL 0 >> +#define FIXUP_TYPE_MC 1 >> + >> #define EX_TYPE_NONE 0 >> #define EX_TYPE_FIXUP 1 >> #define EX_TYPE_BPF 2 >> #define EX_TYPE_UACCESS_ERR_ZERO 3 >> #define EX_TYPE_LOAD_UNALIGNED_ZEROPAD 4 >> >> +/* _MC indicates that can fixup from machine check errors */ >> +#define EX_TYPE_UACCESS_MC 5 >> + >> #ifdef __ASSEMBLY__ >> >> #define __ASM_EXTABLE_RAW(insn, fixup, type, data) \ >> @@ -27,6 +33,14 @@ >> __ASM_EXTABLE_RAW(\insn, \fixup, EX_TYPE_FIXUP, 0) >> .endm >> >> +/* >> + * Create an exception table entry for `insn`, which will branch to `fixup` >> + * when an unhandled fault(include sea fault) is taken. >> + */ >> + .macro _asm_extable_uaccess_mc, insn, fixup >> + __ASM_EXTABLE_RAW(\insn, \fixup, EX_TYPE_UACCESS_MC, 0) >> + .endm >> + >> /* >> * Create an exception table entry for `insn` if `fixup` is provided. Otherwise >> * do nothing. >> diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h >> index 0557af834e03..6c23c138e1fc 100644 >> --- a/arch/arm64/include/asm/asm-uaccess.h >> +++ b/arch/arm64/include/asm/asm-uaccess.h >> @@ -63,6 +63,11 @@ alternative_else_nop_endif >> 9999: x; \ >> _asm_extable 9999b, l >> >> + >> +#define USER_MC(l, x...) \ >> +9999: x; \ >> + _asm_extable_uaccess_mc 9999b, l >> + >> /* >> * Generate the assembly for LDTR/STTR with exception table entries. >> * This is complicated as there is no post-increment or pair versions of the >> @@ -73,8 +78,8 @@ alternative_else_nop_endif >> 8889: ldtr \reg2, [\addr, #8]; >> add \addr, \addr, \post_inc; >> >> - _asm_extable 8888b,\l; >> - _asm_extable 8889b,\l; >> + _asm_extable_uaccess_mc 8888b, \l; >> + _asm_extable_uaccess_mc 8889b, \l; >> .endm >> >> .macro user_stp l, reg1, reg2, addr, post_inc >> @@ -82,14 +87,14 @@ alternative_else_nop_endif >> 8889: sttr \reg2, [\addr, #8]; >> add \addr, \addr, \post_inc; >> >> - _asm_extable 8888b,\l; >> - _asm_extable 8889b,\l; >> + _asm_extable_uaccess_mc 8888b,\l; >> + _asm_extable_uaccess_mc 8889b,\l; >> .endm >> >> .macro user_ldst l, inst, reg, addr, post_inc >> 8888: \inst \reg, [\addr]; >> add \addr, \addr, \post_inc; >> >> - _asm_extable 8888b,\l; >> + _asm_extable_uaccess_mc 8888b, \l; >> .endm >> #endif >> diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_user.S >> index 34e317907524..480cc5ac0a8d 100644 >> --- a/arch/arm64/lib/copy_from_user.S >> +++ b/arch/arm64/lib/copy_from_user.S >> @@ -25,7 +25,7 @@ >> .endm >> >> .macro strb1 reg, ptr, val >> - strb \reg, [\ptr], \val >> + USER_MC(9998f, strb \reg, [\ptr], \val) >> .endm >> >> .macro ldrh1 reg, ptr, val >> @@ -33,7 +33,7 @@ >> .endm >> >> .macro strh1 reg, ptr, val >> - strh \reg, [\ptr], \val >> + USER_MC(9998f, strh \reg, [\ptr], \val) >> .endm >> >> .macro ldr1 reg, ptr, val >> @@ -41,7 +41,7 @@ >> .endm >> >> .macro str1 reg, ptr, val >> - str \reg, [\ptr], \val >> + USER_MC(9998f, str \reg, [\ptr], \val) >> .endm >> >> .macro ldp1 reg1, reg2, ptr, val >> @@ -49,11 +49,12 @@ >> .endm >> >> .macro stp1 reg1, reg2, ptr, val >> - stp \reg1, \reg2, [\ptr], \val >> + USER_MC(9998f, stp \reg1, \reg2, [\ptr], \val) >> .endm >> >> -end .req x5 >> -srcin .req x15 >> +end .req x5 >> +srcin .req x15 >> +fixup_type .req x16 >> SYM_FUNC_START(__arch_copy_from_user) >> add end, x0, x2 >> mov srcin, x1 >> @@ -62,7 +63,10 @@ SYM_FUNC_START(__arch_copy_from_user) >> ret >> >> // Exception fixups >> -9997: cmp dst, dstin >> + // x16: fixup type written by ex_handler_uaccess_mc >> +9997: cmp fixup_type, #FIXUP_TYPE_MC >> + b.eq 9998f >> + cmp dst, dstin >> b.ne 9998f >> // Before being absolutely sure we couldn't copy anything, try harder >> USER(9998f, ldtrb tmp1w, [srcin]) >> diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S >> index 802231772608..021a7d27b3a4 100644 >> --- a/arch/arm64/lib/copy_to_user.S >> +++ b/arch/arm64/lib/copy_to_user.S >> @@ -20,7 +20,7 @@ >> * x0 - bytes not copied >> */ >> .macro ldrb1 reg, ptr, val >> - ldrb \reg, [\ptr], \val >> + USER_MC(9998f, ldrb \reg, [\ptr], \val) >> .endm >> >> .macro strb1 reg, ptr, val >> @@ -28,7 +28,7 @@ >> .endm >> >> .macro ldrh1 reg, ptr, val >> - ldrh \reg, [\ptr], \val >> + USER_MC(9998f, ldrh \reg, [\ptr], \val) >> .endm >> >> .macro strh1 reg, ptr, val >> @@ -36,7 +36,7 @@ >> .endm >> >> .macro ldr1 reg, ptr, val >> - ldr \reg, [\ptr], \val >> + USER_MC(9998f, ldr \reg, [\ptr], \val) >> .endm >> >> .macro str1 reg, ptr, val >> @@ -44,15 +44,16 @@ >> .endm >> >> .macro ldp1 reg1, reg2, ptr, val >> - ldp \reg1, \reg2, [\ptr], \val >> + USER_MC(9998f, ldp \reg1, \reg2, [\ptr], \val) >> .endm >> >> .macro stp1 reg1, reg2, ptr, val >> user_stp 9997f, \reg1, \reg2, \ptr, \val >> .endm >> >> -end .req x5 >> -srcin .req x15 >> +end .req x5 >> +srcin .req x15 >> +fixup_type .req x16 >> SYM_FUNC_START(__arch_copy_to_user) >> add end, x0, x2 >> mov srcin, x1 >> @@ -61,7 +62,10 @@ SYM_FUNC_START(__arch_copy_to_user) >> ret >> >> // Exception fixups >> -9997: cmp dst, dstin >> + // x16: fixup type written by ex_handler_uaccess_mc >> +9997: cmp fixup_type, #FIXUP_TYPE_MC >> + b.eq 9998f >> + cmp dst, dstin >> b.ne 9998f >> // Before being absolutely sure we couldn't copy anything, try harder >> ldrb tmp1w, [srcin] >> diff --git a/arch/arm64/mm/extable.c b/arch/arm64/mm/extable.c >> index 4f0083a550d4..525876c3ebf4 100644 >> --- a/arch/arm64/mm/extable.c >> +++ b/arch/arm64/mm/extable.c >> @@ -24,6 +24,14 @@ static bool ex_handler_fixup(const struct exception_table_entry *ex, >> return true; >> } >> >> +static bool ex_handler_uaccess_type(const struct exception_table_entry *ex, >> + struct pt_regs *regs, >> + unsigned long fixup_type) >> +{ >> + regs->regs[16] = fixup_type; >> + return ex_handler_fixup(ex, regs); >> +} >> + >> static bool ex_handler_uaccess_err_zero(const struct exception_table_entry *ex, >> struct pt_regs *regs) >> { >> @@ -75,6 +83,8 @@ bool fixup_exception(struct pt_regs *regs) >> switch (ex->type) { >> case EX_TYPE_FIXUP: >> return ex_handler_fixup(ex, regs); >> + case EX_TYPE_UACCESS_MC: >> + return ex_handler_uaccess_type(ex, regs, FIXUP_TYPE_NORMAL); >> case EX_TYPE_BPF: >> return ex_handler_bpf(ex, regs); >> case EX_TYPE_UACCESS_ERR_ZERO: >> @@ -94,10 +104,10 @@ bool fixup_exception_mc(struct pt_regs *regs) >> if (!ex) >> return false; >> >> - /* >> - * This is not complete, More Machine check safe extable type can >> - * be processed here. >> - */ >> + switch (ex->type) { >> + case EX_TYPE_UACCESS_MC: >> + return ex_handler_uaccess_type(ex, regs, FIXUP_TYPE_MC); >> + } >> >> return false; >> } >> -- >> 2.25.1 >> > . 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Peter Anvin" , , , , , Kefeng Wang , Xie XiuQi , Guohanjun References: <20220420030418.3189040-1-tongtiangen@huawei.com> <20220420030418.3189040-5-tongtiangen@huawei.com> From: Tong Tiangen In-Reply-To: X-Originating-IP: [10.174.179.234] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemm600017.china.huawei.com (7.193.23.234) X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220518_235323_674285_C94B44B2 X-CRM114-Status: GOOD ( 26.57 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: base64 Content-Type: text/plain; charset="utf-8"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CgrlnKggMjAyMi81LzEzIDIzOjMxLCBNYXJrIFJ1dGxhbmQg5YaZ6YGTOgo+IE9uIFdlZCwgQXBy IDIwLCAyMDIyIGF0IDAzOjA0OjE1QU0gKzAwMDAsIFRvbmcgVGlhbmdlbiB3cm90ZToKPj4gQWRk IGNvcHlfe3RvLCBmcm9tfV91c2VyKCkgdG8gbWFjaGluZSBjaGVjayBzYWZlLgo+Pgo+PiBJZiBj b3B5IGZhaWwgZHVlIHRvIGhhcmR3YXJlIG1lbW9yeSBlcnJvciwgb25seSB0aGUgcmVsZXZhbnQg cHJvY2Vzc2VzIGFyZQo+PiBhZmZlY3RlZCwgc28ga2lsbGluZyB0aGUgdXNlciBwcm9jZXNzIGFu ZCBpc29sYXRlIHRoZSB1c2VyIHBhZ2Ugd2l0aAo+PiBoYXJkd2FyZSBtZW1vcnkgZXJyb3JzIGlz IGEgbW9yZSByZWFzb25hYmxlIGNob2ljZSB0aGFuIGtlcm5lbCBwYW5pYy4KPj4KPj4gQWRkIG5l dyBleHRhYmxlIHR5cGUgRVhfVFlQRV9VQUNDRVNTX01DIHdoaWNoIGNhbiBiZSB1c2VkIGZvciB1 YWNjZXNzIHRoYXQKPj4gY2FuIGJlIHJlY292ZXJlZCBmcm9tIGhhcmR3YXJlIG1lbW9yeSBlcnJv cnMuCj4gCj4gSSBkb24ndCB1bmRlcnN0YW5kIHdoeSB3ZSBuZWVkIHRoaXMuCj4gCj4gSWYgd2Ug YXBwbHkgRVhfVFlQRV9VQUNDRVNTIGNvbnNpc3RlbnRseSB0byAqYWxsKiB1c2VyIGFjY2Vzc2Vz LCBhbmQKPiAqb25seSogdG8gdXNlciBhY2Nlc3NlcywgdGhhdCB3b3VsZCAqYWx3YXlzKiBpbmRp Y2F0ZSB0aGF0IHdlIGNhbgo+IHJlY292ZXIsIGFuZCB0aGF0IHNlZW1zIG11Y2ggc2ltcGxlciB0 byBkZWFsIHdpdGguCj4gCj4gVG9kYXkgd2UgdXNlIEVYX1RZUEVfVUFDQ0VTU19FUlJfWkVSTyBm b3Iga2VybmVsIGFjY2Vzc2VzIGluIGEgY291cGxlIG9mCj4gY2FzZXMsIHdoaWNoIHdlIHNob3Vs ZCBjbGVhbiB1cCwgYW5kIHdlIHVzZXIgRVhfVFlQRV9GSVhVUCBmb3IgYSBjb3VwbGUKPiBvZiB1 c2VyIGFjY2Vzc2VzLCBidXQgdGhvc2UgY291bGQgZWFzaWx5IGJlIGNvbnZlcnRlZCBvdmVyLgo+ IAo+PiBUaGUgeDE2IHJlZ2lzdGVyIGlzIHVzZWQgdG8gc2F2ZSB0aGUgZml4dXAgdHlwZSBpbiBj b3B5X3h4eF91c2VyIHdoaWNoCj4+IHVzZWQgZXh0YWJsZSB0eXBlIEVYX1RZUEVfVUFDQ0VTU19N Qy4KClRoaXMgaXMgZGljdXNzZWQgb24gcGF0Y2ggcGF0Y2ggMy83LgoKPiAKPiBXaHkgeDE2Pwo+ IAo+IEhvdyBpcyB0aGlzIGludGVuZGVkIHRvIGJlIGNvbnN1bWVkLCBhbmQgd2h5IGlzIHRoYXQg YmVoYXZpb3VyIGRpZmZlcmVudAo+IGZyb20gYW55ICpvdGhlciogZmF1bHQ/Cj4gCj4gTWFyay4K ClRoaXMgaXMgdG8gZGlzdGluZ3Vpc2ggRVhfVFlQRV9GSVhVUCwgaWYgdGhpcyBleGNlcHRpb24g aXMgdHJpZ2dlcmVkLCAKaW4gZml4dXAgcHJvY2Vzc2luZywgaXQgaXMgbmVlZGVkIHRvIGNvcHkg YnkgYnl0ZSwgYnV0IGlmIGV4Y2VwdGlvbiBpcyAKdHJpZ2dlcmVkIGJ5IG1hY2hpbmUgY2hlY2ss IHRoZSBkYXRhIGRvZXMgbm90IG5lZWQgdG8gYmUgY29waWVkIGFnYWluLgoKU28gd2UgbmVlZCBv bmUgcGxhY2UgdG8gc3RvcmUgZXhjZXB0aW9uIHR5cGUsIFRoZXJlZm9yZSwgWDE2IHRoYXQgaXMg bm90IApjdXJyZW50bHkgdXNlZCBpbiBjb3B5X2Zyb20vdG9fdXNlciBpcyBzZWxlY3RlZC4KCk1h eWJlIGJldHRlciB0byB1c2UgZXhjZXB0aW9uX3RhYmxlX2VudHJ5LT5kYXRhIHRvIHBhc3MgdGhl IHJlZ2lzdGVyIAp0aGF0IG5lZWRzIHRvIGJlIHNldD8KClRoYW5rcywKVG9uZy4KCgo+IAo+PiBT aWduZWQtb2ZmLWJ5OiBUb25nIFRpYW5nZW4gPHRvbmd0aWFuZ2VuQGh1YXdlaS5jb20+Cj4+IC0t LQo+PiAgIGFyY2gvYXJtNjQvaW5jbHVkZS9hc20vYXNtLWV4dGFibGUuaCB8IDE0ICsrKysrKysr KysrKysrCj4+ICAgYXJjaC9hcm02NC9pbmNsdWRlL2FzbS9hc20tdWFjY2Vzcy5oIHwgMTUgKysr KysrKysrKy0tLS0tCj4+ICAgYXJjaC9hcm02NC9saWIvY29weV9mcm9tX3VzZXIuUyAgICAgIHwg MTggKysrKysrKysrKystLS0tLS0tCj4+ICAgYXJjaC9hcm02NC9saWIvY29weV90b191c2VyLlMg ICAgICAgIHwgMTggKysrKysrKysrKystLS0tLS0tCj4+ICAgYXJjaC9hcm02NC9tbS9leHRhYmxl LmMgICAgICAgICAgICAgIHwgMTggKysrKysrKysrKysrKystLS0tCj4+ICAgNSBmaWxlcyBjaGFu Z2VkLCA2MCBpbnNlcnRpb25zKCspLCAyMyBkZWxldGlvbnMoLSkKPj4KPj4gZGlmZiAtLWdpdCBh L2FyY2gvYXJtNjQvaW5jbHVkZS9hc20vYXNtLWV4dGFibGUuaCBiL2FyY2gvYXJtNjQvaW5jbHVk ZS9hc20vYXNtLWV4dGFibGUuaAo+PiBpbmRleCBjMzlmMjQzN2UwOGUuLjc1YjJjMDBlOTUyMyAx MDA2NDQKPj4gLS0tIGEvYXJjaC9hcm02NC9pbmNsdWRlL2FzbS9hc20tZXh0YWJsZS5oCj4+ICsr KyBiL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20vYXNtLWV4dGFibGUuaAo+PiBAQCAtMiwxMiArMiwx OCBAQAo+PiAgICNpZm5kZWYgX19BU01fQVNNX0VYVEFCTEVfSAo+PiAgICNkZWZpbmUgX19BU01f QVNNX0VYVEFCTEVfSAo+PiAgIAo+PiArI2RlZmluZSBGSVhVUF9UWVBFX05PUk1BTAkJMAo+PiAr I2RlZmluZSBGSVhVUF9UWVBFX01DCQkJMQo+PiArCj4+ICAgI2RlZmluZSBFWF9UWVBFX05PTkUJ CQkwCj4+ICAgI2RlZmluZSBFWF9UWVBFX0ZJWFVQCQkJMQo+PiAgICNkZWZpbmUgRVhfVFlQRV9C UEYJCQkyCj4+ICAgI2RlZmluZSBFWF9UWVBFX1VBQ0NFU1NfRVJSX1pFUk8JMwo+PiAgICNkZWZp bmUgRVhfVFlQRV9MT0FEX1VOQUxJR05FRF9aRVJPUEFECTQKPj4gICAKPj4gKy8qIF9NQyBpbmRp Y2F0ZXMgdGhhdCBjYW4gZml4dXAgZnJvbSBtYWNoaW5lIGNoZWNrIGVycm9ycyAqLwo+PiArI2Rl ZmluZSBFWF9UWVBFX1VBQ0NFU1NfTUMJCTUKPj4gKwo+PiAgICNpZmRlZiBfX0FTU0VNQkxZX18K Pj4gICAKPj4gICAjZGVmaW5lIF9fQVNNX0VYVEFCTEVfUkFXKGluc24sIGZpeHVwLCB0eXBlLCBk YXRhKQlcCj4+IEBAIC0yNyw2ICszMywxNCBAQAo+PiAgIAlfX0FTTV9FWFRBQkxFX1JBVyhcaW5z biwgXGZpeHVwLCBFWF9UWVBFX0ZJWFVQLCAwKQo+PiAgIAkuZW5kbQo+PiAgIAo+PiArLyoKPj4g KyAqIENyZWF0ZSBhbiBleGNlcHRpb24gdGFibGUgZW50cnkgZm9yIGBpbnNuYCwgd2hpY2ggd2ls bCBicmFuY2ggdG8gYGZpeHVwYAo+PiArICogd2hlbiBhbiB1bmhhbmRsZWQgZmF1bHQoaW5jbHVk ZSBzZWEgZmF1bHQpIGlzIHRha2VuLgo+PiArICovCj4+ICsJLm1hY3JvICAgICAgICAgIF9hc21f ZXh0YWJsZV91YWNjZXNzX21jLCBpbnNuLCBmaXh1cAo+PiArCV9fQVNNX0VYVEFCTEVfUkFXKFxp bnNuLCBcZml4dXAsIEVYX1RZUEVfVUFDQ0VTU19NQywgMCkKPj4gKwkuZW5kbQo+PiArCj4+ICAg LyoKPj4gICAgKiBDcmVhdGUgYW4gZXhjZXB0aW9uIHRhYmxlIGVudHJ5IGZvciBgaW5zbmAgaWYg YGZpeHVwYCBpcyBwcm92aWRlZC4gT3RoZXJ3aXNlCj4+ICAgICogZG8gbm90aGluZy4KPj4gZGlm ZiAtLWdpdCBhL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20vYXNtLXVhY2Nlc3MuaCBiL2FyY2gvYXJt NjQvaW5jbHVkZS9hc20vYXNtLXVhY2Nlc3MuaAo+PiBpbmRleCAwNTU3YWY4MzRlMDMuLjZjMjNj MTM4ZTFmYyAxMDA2NDQKPj4gLS0tIGEvYXJjaC9hcm02NC9pbmNsdWRlL2FzbS9hc20tdWFjY2Vz cy5oCj4+ICsrKyBiL2FyY2gvYXJtNjQvaW5jbHVkZS9hc20vYXNtLXVhY2Nlc3MuaAo+PiBAQCAt NjMsNiArNjMsMTEgQEAgYWx0ZXJuYXRpdmVfZWxzZV9ub3BfZW5kaWYKPj4gICA5OTk5Ogl4OwkJ CQkJXAo+PiAgIAlfYXNtX2V4dGFibGUJOTk5OWIsIGwKPj4gICAKPj4gKwo+PiArI2RlZmluZSBV U0VSX01DKGwsIHguLi4pCQkJXAo+PiArOTk5OToJeDsJCQkJCVwKPj4gKwlfYXNtX2V4dGFibGVf dWFjY2Vzc19tYwk5OTk5YiwgbAo+PiArCj4+ICAgLyoKPj4gICAgKiBHZW5lcmF0ZSB0aGUgYXNz ZW1ibHkgZm9yIExEVFIvU1RUUiB3aXRoIGV4Y2VwdGlvbiB0YWJsZSBlbnRyaWVzLgo+PiAgICAq IFRoaXMgaXMgY29tcGxpY2F0ZWQgYXMgdGhlcmUgaXMgbm8gcG9zdC1pbmNyZW1lbnQgb3IgcGFp ciB2ZXJzaW9ucyBvZiB0aGUKPj4gQEAgLTczLDggKzc4LDggQEAgYWx0ZXJuYXRpdmVfZWxzZV9u b3BfZW5kaWYKPj4gICA4ODg5OgkJbGR0cglccmVnMiwgW1xhZGRyLCAjOF07Cj4+ICAgCQlhZGQJ XGFkZHIsIFxhZGRyLCBccG9zdF9pbmM7Cj4+ICAgCj4+IC0JCV9hc21fZXh0YWJsZQk4ODg4Yixc bDsKPj4gLQkJX2FzbV9leHRhYmxlCTg4ODliLFxsOwo+PiArCQlfYXNtX2V4dGFibGVfdWFjY2Vz c19tYwk4ODg4YiwgXGw7Cj4+ICsJCV9hc21fZXh0YWJsZV91YWNjZXNzX21jCTg4ODliLCBcbDsK Pj4gICAJLmVuZG0KPj4gICAKPj4gICAJLm1hY3JvIHVzZXJfc3RwIGwsIHJlZzEsIHJlZzIsIGFk ZHIsIHBvc3RfaW5jCj4+IEBAIC04MiwxNCArODcsMTQgQEAgYWx0ZXJuYXRpdmVfZWxzZV9ub3Bf ZW5kaWYKPj4gICA4ODg5OgkJc3R0cglccmVnMiwgW1xhZGRyLCAjOF07Cj4+ICAgCQlhZGQJXGFk ZHIsIFxhZGRyLCBccG9zdF9pbmM7Cj4+ICAgCj4+IC0JCV9hc21fZXh0YWJsZQk4ODg4YixcbDsK Pj4gLQkJX2FzbV9leHRhYmxlCTg4ODliLFxsOwo+PiArCQlfYXNtX2V4dGFibGVfdWFjY2Vzc19t Ywk4ODg4YixcbDsKPj4gKwkJX2FzbV9leHRhYmxlX3VhY2Nlc3NfbWMJODg4OWIsXGw7Cj4+ICAg CS5lbmRtCj4+ICAgCj4+ICAgCS5tYWNybyB1c2VyX2xkc3QgbCwgaW5zdCwgcmVnLCBhZGRyLCBw b3N0X2luYwo+PiAgIDg4ODg6CQlcaW5zdAkJXHJlZywgW1xhZGRyXTsKPj4gICAJCWFkZAkJXGFk ZHIsIFxhZGRyLCBccG9zdF9pbmM7Cj4+ICAgCj4+IC0JCV9hc21fZXh0YWJsZQk4ODg4YixcbDsK Pj4gKwkJX2FzbV9leHRhYmxlX3VhY2Nlc3NfbWMJODg4OGIsIFxsOwo+PiAgIAkuZW5kbQo+PiAg ICNlbmRpZgo+PiBkaWZmIC0tZ2l0IGEvYXJjaC9hcm02NC9saWIvY29weV9mcm9tX3VzZXIuUyBi L2FyY2gvYXJtNjQvbGliL2NvcHlfZnJvbV91c2VyLlMKPj4gaW5kZXggMzRlMzE3OTA3NTI0Li40 ODBjYzVhYzBhOGQgMTAwNjQ0Cj4+IC0tLSBhL2FyY2gvYXJtNjQvbGliL2NvcHlfZnJvbV91c2Vy LlMKPj4gKysrIGIvYXJjaC9hcm02NC9saWIvY29weV9mcm9tX3VzZXIuUwo+PiBAQCAtMjUsNyAr MjUsNyBAQAo+PiAgIAkuZW5kbQo+PiAgIAo+PiAgIAkubWFjcm8gc3RyYjEgcmVnLCBwdHIsIHZh bAo+PiAtCXN0cmIgXHJlZywgW1xwdHJdLCBcdmFsCj4+ICsJVVNFUl9NQyg5OTk4Ziwgc3RyYiBc cmVnLCBbXHB0cl0sIFx2YWwpCj4+ICAgCS5lbmRtCj4+ICAgCj4+ICAgCS5tYWNybyBsZHJoMSBy ZWcsIHB0ciwgdmFsCj4+IEBAIC0zMyw3ICszMyw3IEBACj4+ICAgCS5lbmRtCj4+ICAgCj4+ICAg CS5tYWNybyBzdHJoMSByZWcsIHB0ciwgdmFsCj4+IC0Jc3RyaCBccmVnLCBbXHB0cl0sIFx2YWwK Pj4gKwlVU0VSX01DKDk5OThmLCBzdHJoIFxyZWcsIFtccHRyXSwgXHZhbCkKPj4gICAJLmVuZG0K Pj4gICAKPj4gICAJLm1hY3JvIGxkcjEgcmVnLCBwdHIsIHZhbAo+PiBAQCAtNDEsNyArNDEsNyBA QAo+PiAgIAkuZW5kbQo+PiAgIAo+PiAgIAkubWFjcm8gc3RyMSByZWcsIHB0ciwgdmFsCj4+IC0J c3RyIFxyZWcsIFtccHRyXSwgXHZhbAo+PiArCVVTRVJfTUMoOTk5OGYsIHN0ciBccmVnLCBbXHB0 cl0sIFx2YWwpCj4+ICAgCS5lbmRtCj4+ICAgCj4+ICAgCS5tYWNybyBsZHAxIHJlZzEsIHJlZzIs IHB0ciwgdmFsCj4+IEBAIC00OSwxMSArNDksMTIgQEAKPj4gICAJLmVuZG0KPj4gICAKPj4gICAJ Lm1hY3JvIHN0cDEgcmVnMSwgcmVnMiwgcHRyLCB2YWwKPj4gLQlzdHAgXHJlZzEsIFxyZWcyLCBb XHB0cl0sIFx2YWwKPj4gKwlVU0VSX01DKDk5OThmLCBzdHAgXHJlZzEsIFxyZWcyLCBbXHB0cl0s IFx2YWwpCj4+ICAgCS5lbmRtCj4+ICAgCj4+IC1lbmQJLnJlcQl4NQo+PiAtc3JjaW4JLnJlcQl4 MTUKPj4gK2VuZAkJLnJlcQl4NQo+PiArc3JjaW4JCS5yZXEJeDE1Cj4+ICtmaXh1cF90eXBlCS5y ZXEJeDE2Cj4+ICAgU1lNX0ZVTkNfU1RBUlQoX19hcmNoX2NvcHlfZnJvbV91c2VyKQo+PiAgIAlh ZGQJZW5kLCB4MCwgeDIKPj4gICAJbW92CXNyY2luLCB4MQo+PiBAQCAtNjIsNyArNjMsMTAgQEAg U1lNX0ZVTkNfU1RBUlQoX19hcmNoX2NvcHlfZnJvbV91c2VyKQo+PiAgIAlyZXQKPj4gICAKPj4g ICAJLy8gRXhjZXB0aW9uIGZpeHVwcwo+PiAtOTk5NzoJY21wCWRzdCwgZHN0aW4KPj4gKwkvLyB4 MTY6IGZpeHVwIHR5cGUgd3JpdHRlbiBieSBleF9oYW5kbGVyX3VhY2Nlc3NfbWMKPj4gKzk5OTc6 CWNtcCAJZml4dXBfdHlwZSwgI0ZJWFVQX1RZUEVfTUMKPj4gKwliLmVxCTk5OThmCj4+ICsJY21w CWRzdCwgZHN0aW4KPj4gICAJYi5uZQk5OTk4Zgo+PiAgIAkvLyBCZWZvcmUgYmVpbmcgYWJzb2x1 dGVseSBzdXJlIHdlIGNvdWxkbid0IGNvcHkgYW55dGhpbmcsIHRyeSBoYXJkZXIKPj4gICBVU0VS KDk5OThmLCBsZHRyYiB0bXAxdywgW3NyY2luXSkKPj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtNjQv bGliL2NvcHlfdG9fdXNlci5TIGIvYXJjaC9hcm02NC9saWIvY29weV90b191c2VyLlMKPj4gaW5k ZXggODAyMjMxNzcyNjA4Li4wMjFhN2QyN2IzYTQgMTAwNjQ0Cj4+IC0tLSBhL2FyY2gvYXJtNjQv bGliL2NvcHlfdG9fdXNlci5TCj4+ICsrKyBiL2FyY2gvYXJtNjQvbGliL2NvcHlfdG9fdXNlci5T Cj4+IEBAIC0yMCw3ICsyMCw3IEBACj4+ICAgICoJeDAgLSBieXRlcyBub3QgY29waWVkCj4+ICAg ICovCj4+ICAgCS5tYWNybyBsZHJiMSByZWcsIHB0ciwgdmFsCj4+IC0JbGRyYiAgXHJlZywgW1xw dHJdLCBcdmFsCj4+ICsJVVNFUl9NQyg5OTk4ZiwgbGRyYiAgXHJlZywgW1xwdHJdLCBcdmFsKQo+ PiAgIAkuZW5kbQo+PiAgIAo+PiAgIAkubWFjcm8gc3RyYjEgcmVnLCBwdHIsIHZhbAo+PiBAQCAt MjgsNyArMjgsNyBAQAo+PiAgIAkuZW5kbQo+PiAgIAo+PiAgIAkubWFjcm8gbGRyaDEgcmVnLCBw dHIsIHZhbAo+PiAtCWxkcmggIFxyZWcsIFtccHRyXSwgXHZhbAo+PiArCVVTRVJfTUMoOTk5OGYs IGxkcmggIFxyZWcsIFtccHRyXSwgXHZhbCkKPj4gICAJLmVuZG0KPj4gICAKPj4gICAJLm1hY3Jv IHN0cmgxIHJlZywgcHRyLCB2YWwKPj4gQEAgLTM2LDcgKzM2LDcgQEAKPj4gICAJLmVuZG0KPj4g ICAKPj4gICAJLm1hY3JvIGxkcjEgcmVnLCBwdHIsIHZhbAo+PiAtCWxkciBccmVnLCBbXHB0cl0s IFx2YWwKPj4gKwlVU0VSX01DKDk5OThmLCBsZHIgXHJlZywgW1xwdHJdLCBcdmFsKQo+PiAgIAku ZW5kbQo+PiAgIAo+PiAgIAkubWFjcm8gc3RyMSByZWcsIHB0ciwgdmFsCj4+IEBAIC00NCwxNSAr NDQsMTYgQEAKPj4gICAJLmVuZG0KPj4gICAKPj4gICAJLm1hY3JvIGxkcDEgcmVnMSwgcmVnMiwg cHRyLCB2YWwKPj4gLQlsZHAgXHJlZzEsIFxyZWcyLCBbXHB0cl0sIFx2YWwKPj4gKwlVU0VSX01D KDk5OThmLCBsZHAgXHJlZzEsIFxyZWcyLCBbXHB0cl0sIFx2YWwpCj4+ICAgCS5lbmRtCj4+ICAg Cj4+ICAgCS5tYWNybyBzdHAxIHJlZzEsIHJlZzIsIHB0ciwgdmFsCj4+ICAgCXVzZXJfc3RwIDk5 OTdmLCBccmVnMSwgXHJlZzIsIFxwdHIsIFx2YWwKPj4gICAJLmVuZG0KPj4gICAKPj4gLWVuZAku cmVxCXg1Cj4+IC1zcmNpbgkucmVxCXgxNQo+PiArZW5kCQkucmVxCXg1Cj4+ICtzcmNpbgkJLnJl cQl4MTUKPj4gK2ZpeHVwX3R5cGUJLnJlcQl4MTYKPj4gICBTWU1fRlVOQ19TVEFSVChfX2FyY2hf Y29weV90b191c2VyKQo+PiAgIAlhZGQJZW5kLCB4MCwgeDIKPj4gICAJbW92CXNyY2luLCB4MQo+ PiBAQCAtNjEsNyArNjIsMTAgQEAgU1lNX0ZVTkNfU1RBUlQoX19hcmNoX2NvcHlfdG9fdXNlcikK Pj4gICAJcmV0Cj4+ICAgCj4+ICAgCS8vIEV4Y2VwdGlvbiBmaXh1cHMKPj4gLTk5OTc6CWNtcAlk c3QsIGRzdGluCj4+ICsJLy8geDE2OiBmaXh1cCB0eXBlIHdyaXR0ZW4gYnkgZXhfaGFuZGxlcl91 YWNjZXNzX21jCj4+ICs5OTk3OgljbXAgCWZpeHVwX3R5cGUsICNGSVhVUF9UWVBFX01DCj4+ICsJ Yi5lcQk5OTk4Zgo+PiArCWNtcAlkc3QsIGRzdGluCj4+ICAgCWIubmUJOTk5OGYKPj4gICAJLy8g QmVmb3JlIGJlaW5nIGFic29sdXRlbHkgc3VyZSB3ZSBjb3VsZG4ndCBjb3B5IGFueXRoaW5nLCB0 cnkgaGFyZGVyCj4+ICAgCWxkcmIJdG1wMXcsIFtzcmNpbl0KPj4gZGlmZiAtLWdpdCBhL2FyY2gv YXJtNjQvbW0vZXh0YWJsZS5jIGIvYXJjaC9hcm02NC9tbS9leHRhYmxlLmMKPj4gaW5kZXggNGYw MDgzYTU1MGQ0Li41MjU4NzZjM2ViZjQgMTAwNjQ0Cj4+IC0tLSBhL2FyY2gvYXJtNjQvbW0vZXh0 YWJsZS5jCj4+ICsrKyBiL2FyY2gvYXJtNjQvbW0vZXh0YWJsZS5jCj4+IEBAIC0yNCw2ICsyNCwx NCBAQCBzdGF0aWMgYm9vbCBleF9oYW5kbGVyX2ZpeHVwKGNvbnN0IHN0cnVjdCBleGNlcHRpb25f dGFibGVfZW50cnkgKmV4LAo+PiAgIAlyZXR1cm4gdHJ1ZTsKPj4gICB9Cj4+ICAgCj4+ICtzdGF0 aWMgYm9vbCBleF9oYW5kbGVyX3VhY2Nlc3NfdHlwZShjb25zdCBzdHJ1Y3QgZXhjZXB0aW9uX3Rh YmxlX2VudHJ5ICpleCwKPj4gKwkJCSAgICAgc3RydWN0IHB0X3JlZ3MgKnJlZ3MsCj4+ICsJCQkg ICAgIHVuc2lnbmVkIGxvbmcgZml4dXBfdHlwZSkKPj4gK3sKPj4gKwlyZWdzLT5yZWdzWzE2XSA9 IGZpeHVwX3R5cGU7Cj4+ICsJcmV0dXJuIGV4X2hhbmRsZXJfZml4dXAoZXgsIHJlZ3MpOwo+PiAr fQo+PiArCj4+ICAgc3RhdGljIGJvb2wgZXhfaGFuZGxlcl91YWNjZXNzX2Vycl96ZXJvKGNvbnN0 IHN0cnVjdCBleGNlcHRpb25fdGFibGVfZW50cnkgKmV4LAo+PiAgIAkJCQkJc3RydWN0IHB0X3Jl Z3MgKnJlZ3MpCj4+ICAgewo+PiBAQCAtNzUsNiArODMsOCBAQCBib29sIGZpeHVwX2V4Y2VwdGlv bihzdHJ1Y3QgcHRfcmVncyAqcmVncykKPj4gICAJc3dpdGNoIChleC0+dHlwZSkgewo+PiAgIAlj YXNlIEVYX1RZUEVfRklYVVA6Cj4+ICAgCQlyZXR1cm4gZXhfaGFuZGxlcl9maXh1cChleCwgcmVn cyk7Cj4+ICsJY2FzZSBFWF9UWVBFX1VBQ0NFU1NfTUM6Cj4+ICsJCXJldHVybiBleF9oYW5kbGVy X3VhY2Nlc3NfdHlwZShleCwgcmVncywgRklYVVBfVFlQRV9OT1JNQUwpOwo+PiAgIAljYXNlIEVY X1RZUEVfQlBGOgo+PiAgIAkJcmV0dXJuIGV4X2hhbmRsZXJfYnBmKGV4LCByZWdzKTsKPj4gICAJ Y2FzZSBFWF9UWVBFX1VBQ0NFU1NfRVJSX1pFUk86Cj4+IEBAIC05NCwxMCArMTA0LDEwIEBAIGJv b2wgZml4dXBfZXhjZXB0aW9uX21jKHN0cnVjdCBwdF9yZWdzICpyZWdzKQo+PiAgIAlpZiAoIWV4 KQo+PiAgIAkJcmV0dXJuIGZhbHNlOwo+PiAgIAo+PiAtCS8qCj4+IC0JICogVGhpcyBpcyBub3Qg Y29tcGxldGUsIE1vcmUgTWFjaGluZSBjaGVjayBzYWZlIGV4dGFibGUgdHlwZSBjYW4KPj4gLQkg KiBiZSBwcm9jZXNzZWQgaGVyZS4KPj4gLQkgKi8KPj4gKwlzd2l0Y2ggKGV4LT50eXBlKSB7Cj4+ ICsJY2FzZSBFWF9UWVBFX1VBQ0NFU1NfTUM6Cj4+ICsJCXJldHVybiBleF9oYW5kbGVyX3VhY2Nl c3NfdHlwZShleCwgcmVncywgRklYVVBfVFlQRV9NQyk7Cj4+ICsJfQo+PiAgIAo+PiAgIAlyZXR1 cm4gZmFsc2U7Cj4+ICAgfQo+PiAtLSAKPj4gMi4yNS4xCj4+Cj4gLgoKX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGludXgtYXJtLWtlcm5lbCBtYWlsaW5n IGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5p bmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtYXJtLWtlcm5lbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from kanga.kvack.org (kanga.kvack.org [205.233.56.17]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2D79C433EF for ; Thu, 19 May 2022 06:53:22 +0000 (UTC) Received: by kanga.kvack.org (Postfix) id 5E1406B0072; Thu, 19 May 2022 02:53:22 -0400 (EDT) Received: by kanga.kvack.org (Postfix, from userid 40) id 58F8D6B0073; Thu, 19 May 2022 02:53:22 -0400 (EDT) X-Delivered-To: int-list-linux-mm@kvack.org Received: by kanga.kvack.org (Postfix, from userid 63042) id 47FF56B0074; Thu, 19 May 2022 02:53:22 -0400 (EDT) X-Delivered-To: linux-mm@kvack.org Received: from relay.hostedemail.com (smtprelay0017.hostedemail.com [216.40.44.17]) by kanga.kvack.org (Postfix) with ESMTP id 39D6D6B0072 for ; Thu, 19 May 2022 02:53:22 -0400 (EDT) Received: from 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15.1.2375.24; Thu, 19 May 2022 14:53:15 +0800 Message-ID: Date: Thu, 19 May 2022 14:53:14 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.8.0 Subject: Re: [PATCH -next v4 4/7] arm64: add copy_{to, from}_user to machine check safe To: Mark Rutland CC: James Morse , Andrew Morton , Thomas Gleixner , "Ingo Molnar" , Borislav Petkov , Robin Murphy , Dave Hansen , "Catalin Marinas" , Will Deacon , "Alexander Viro" , Michael Ellerman , Benjamin Herrenschmidt , Paul Mackerras , , "H . Peter Anvin" , , , , , Kefeng Wang , Xie XiuQi , Guohanjun References: <20220420030418.3189040-1-tongtiangen@huawei.com> <20220420030418.3189040-5-tongtiangen@huawei.com> From: Tong Tiangen In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.174.179.234] X-ClientProxiedBy: dggems704-chm.china.huawei.com (10.3.19.181) To kwepemm600017.china.huawei.com (7.193.23.234) X-CFilter-Loop: Reflected X-Rspam-User: X-Rspamd-Server: rspam11 X-Rspamd-Queue-Id: 5619DC00E1 X-Stat-Signature: 9ffbzth4putpef9iccmn9prce1cinkr6 Authentication-Results: imf22.hostedemail.com; dkim=none; dmarc=pass (policy=quarantine) header.from=huawei.com; spf=pass (imf22.hostedemail.com: domain of tongtiangen@huawei.com designates 45.249.212.188 as permitted sender) smtp.mailfrom=tongtiangen@huawei.com X-HE-Tag: 1652943198-291076 X-Bogosity: Ham, tests=bogofilter, spamicity=0.000000, version=1.2.4 Sender: owner-linux-mm@kvack.org Precedence: bulk X-Loop: owner-majordomo@kvack.org List-ID: 在 2022/5/13 23:31, Mark Rutland 写道: > On Wed, Apr 20, 2022 at 03:04:15AM +0000, Tong Tiangen wrote: >> Add copy_{to, from}_user() to machine check safe. >> >> If copy fail due to hardware memory error, only the relevant processes are >> affected, so killing the user process and isolate the user page with >> hardware memory errors is a more reasonable choice than kernel panic. >> >> Add new extable type EX_TYPE_UACCESS_MC which can be used for uaccess that >> can be recovered from hardware memory errors. > > I don't understand why we need this. > > If we apply EX_TYPE_UACCESS consistently to *all* user accesses, and > *only* to user accesses, that would *always* indicate that we can > recover, and that seems much simpler to deal with. > > Today we use EX_TYPE_UACCESS_ERR_ZERO for kernel accesses in a couple of > cases, which we should clean up, and we user EX_TYPE_FIXUP for a couple > of user accesses, but those could easily be converted over. > >> The x16 register is used to save the fixup type in copy_xxx_user which >> used extable type EX_TYPE_UACCESS_MC. This is dicussed on patch patch 3/7. > > Why x16? > > How is this intended to be consumed, and why is that behaviour different > from any *other* fault? > > Mark. This is to distinguish EX_TYPE_FIXUP, if this exception is triggered, in fixup processing, it is needed to copy by byte, but if exception is triggered by machine check, the data does not need to be copied again. So we need one place to store exception type, Therefore, X16 that is not currently used in copy_from/to_user is selected. Maybe better to use exception_table_entry->data to pass the register that needs to be set? Thanks, Tong. > >> Signed-off-by: Tong Tiangen >> --- >> arch/arm64/include/asm/asm-extable.h | 14 ++++++++++++++ >> arch/arm64/include/asm/asm-uaccess.h | 15 ++++++++++----- >> arch/arm64/lib/copy_from_user.S | 18 +++++++++++------- >> arch/arm64/lib/copy_to_user.S | 18 +++++++++++------- >> arch/arm64/mm/extable.c | 18 ++++++++++++++---- >> 5 files changed, 60 insertions(+), 23 deletions(-) >> >> diff --git a/arch/arm64/include/asm/asm-extable.h b/arch/arm64/include/asm/asm-extable.h >> index c39f2437e08e..75b2c00e9523 100644 >> --- a/arch/arm64/include/asm/asm-extable.h >> +++ b/arch/arm64/include/asm/asm-extable.h >> @@ -2,12 +2,18 @@ >> #ifndef __ASM_ASM_EXTABLE_H >> #define __ASM_ASM_EXTABLE_H >> >> +#define FIXUP_TYPE_NORMAL 0 >> +#define FIXUP_TYPE_MC 1 >> + >> #define EX_TYPE_NONE 0 >> #define EX_TYPE_FIXUP 1 >> #define EX_TYPE_BPF 2 >> #define EX_TYPE_UACCESS_ERR_ZERO 3 >> #define EX_TYPE_LOAD_UNALIGNED_ZEROPAD 4 >> >> +/* _MC indicates that can fixup from machine check errors */ >> +#define EX_TYPE_UACCESS_MC 5 >> + >> #ifdef __ASSEMBLY__ >> >> #define __ASM_EXTABLE_RAW(insn, fixup, type, data) \ >> @@ -27,6 +33,14 @@ >> __ASM_EXTABLE_RAW(\insn, \fixup, EX_TYPE_FIXUP, 0) >> .endm >> >> +/* >> + * Create an exception table entry for `insn`, which will branch to `fixup` >> + * when an unhandled fault(include sea fault) is taken. >> + */ >> + .macro _asm_extable_uaccess_mc, insn, fixup >> + __ASM_EXTABLE_RAW(\insn, \fixup, EX_TYPE_UACCESS_MC, 0) >> + .endm >> + >> /* >> * Create an exception table entry for `insn` if `fixup` is provided. Otherwise >> * do nothing. >> diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h >> index 0557af834e03..6c23c138e1fc 100644 >> --- a/arch/arm64/include/asm/asm-uaccess.h >> +++ b/arch/arm64/include/asm/asm-uaccess.h >> @@ -63,6 +63,11 @@ alternative_else_nop_endif >> 9999: x; \ >> _asm_extable 9999b, l >> >> + >> +#define USER_MC(l, x...) \ >> +9999: x; \ >> + _asm_extable_uaccess_mc 9999b, l >> + >> /* >> * Generate the assembly for LDTR/STTR with exception table entries. >> * This is complicated as there is no post-increment or pair versions of the >> @@ -73,8 +78,8 @@ alternative_else_nop_endif >> 8889: ldtr \reg2, [\addr, #8]; >> add \addr, \addr, \post_inc; >> >> - _asm_extable 8888b,\l; >> - _asm_extable 8889b,\l; >> + _asm_extable_uaccess_mc 8888b, \l; >> + _asm_extable_uaccess_mc 8889b, \l; >> .endm >> >> .macro user_stp l, reg1, reg2, addr, post_inc >> @@ -82,14 +87,14 @@ alternative_else_nop_endif >> 8889: sttr \reg2, [\addr, #8]; >> add \addr, \addr, \post_inc; >> >> - _asm_extable 8888b,\l; >> - _asm_extable 8889b,\l; >> + _asm_extable_uaccess_mc 8888b,\l; >> + _asm_extable_uaccess_mc 8889b,\l; >> .endm >> >> .macro user_ldst l, inst, reg, addr, post_inc >> 8888: \inst \reg, [\addr]; >> add \addr, \addr, \post_inc; >> >> - _asm_extable 8888b,\l; >> + _asm_extable_uaccess_mc 8888b, \l; >> .endm >> #endif >> diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_user.S >> index 34e317907524..480cc5ac0a8d 100644 >> --- a/arch/arm64/lib/copy_from_user.S >> +++ b/arch/arm64/lib/copy_from_user.S >> @@ -25,7 +25,7 @@ >> .endm >> >> .macro strb1 reg, ptr, val >> - strb \reg, [\ptr], \val >> + USER_MC(9998f, strb \reg, [\ptr], \val) >> .endm >> >> .macro ldrh1 reg, ptr, val >> @@ -33,7 +33,7 @@ >> .endm >> >> .macro strh1 reg, ptr, val >> - strh \reg, [\ptr], \val >> + USER_MC(9998f, strh \reg, [\ptr], \val) >> .endm >> >> .macro ldr1 reg, ptr, val >> @@ -41,7 +41,7 @@ >> .endm >> >> .macro str1 reg, ptr, val >> - str \reg, [\ptr], \val >> + USER_MC(9998f, str \reg, [\ptr], \val) >> .endm >> >> .macro ldp1 reg1, reg2, ptr, val >> @@ -49,11 +49,12 @@ >> .endm >> >> .macro stp1 reg1, reg2, ptr, val >> - stp \reg1, \reg2, [\ptr], \val >> + USER_MC(9998f, stp \reg1, \reg2, [\ptr], \val) >> .endm >> >> -end .req x5 >> -srcin .req x15 >> +end .req x5 >> +srcin .req x15 >> +fixup_type .req x16 >> SYM_FUNC_START(__arch_copy_from_user) >> add end, x0, x2 >> mov srcin, x1 >> @@ -62,7 +63,10 @@ SYM_FUNC_START(__arch_copy_from_user) >> ret >> >> // Exception fixups >> -9997: cmp dst, dstin >> + // x16: fixup type written by ex_handler_uaccess_mc >> +9997: cmp fixup_type, #FIXUP_TYPE_MC >> + b.eq 9998f >> + cmp dst, dstin >> b.ne 9998f >> // Before being absolutely sure we couldn't copy anything, try harder >> USER(9998f, ldtrb tmp1w, [srcin]) >> diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S >> index 802231772608..021a7d27b3a4 100644 >> --- a/arch/arm64/lib/copy_to_user.S >> +++ b/arch/arm64/lib/copy_to_user.S >> @@ -20,7 +20,7 @@ >> * x0 - bytes not copied >> */ >> .macro ldrb1 reg, ptr, val >> - ldrb \reg, [\ptr], \val >> + USER_MC(9998f, ldrb \reg, [\ptr], \val) >> .endm >> >> .macro strb1 reg, ptr, val >> @@ -28,7 +28,7 @@ >> .endm >> >> .macro ldrh1 reg, ptr, val >> - ldrh \reg, [\ptr], \val >> + USER_MC(9998f, ldrh \reg, [\ptr], \val) >> .endm >> >> .macro strh1 reg, ptr, val >> @@ -36,7 +36,7 @@ >> .endm >> >> .macro ldr1 reg, ptr, val >> - ldr \reg, [\ptr], \val >> + USER_MC(9998f, ldr \reg, [\ptr], \val) >> .endm >> >> .macro str1 reg, ptr, val >> @@ -44,15 +44,16 @@ >> .endm >> >> .macro ldp1 reg1, reg2, ptr, val >> - ldp \reg1, \reg2, [\ptr], \val >> + USER_MC(9998f, ldp \reg1, \reg2, [\ptr], \val) >> .endm >> >> .macro stp1 reg1, reg2, ptr, val >> user_stp 9997f, \reg1, \reg2, \ptr, \val >> .endm >> >> -end .req x5 >> -srcin .req x15 >> +end .req x5 >> +srcin .req x15 >> +fixup_type .req x16 >> SYM_FUNC_START(__arch_copy_to_user) >> add end, x0, x2 >> mov srcin, x1 >> @@ -61,7 +62,10 @@ SYM_FUNC_START(__arch_copy_to_user) >> ret >> >> // Exception fixups >> -9997: cmp dst, dstin >> + // x16: fixup type written by ex_handler_uaccess_mc >> +9997: cmp fixup_type, #FIXUP_TYPE_MC >> + b.eq 9998f >> + cmp dst, dstin >> b.ne 9998f >> // Before being absolutely sure we couldn't copy anything, try harder >> ldrb tmp1w, [srcin] >> diff --git a/arch/arm64/mm/extable.c b/arch/arm64/mm/extable.c >> index 4f0083a550d4..525876c3ebf4 100644 >> --- a/arch/arm64/mm/extable.c >> +++ b/arch/arm64/mm/extable.c >> @@ -24,6 +24,14 @@ static bool ex_handler_fixup(const struct exception_table_entry *ex, >> return true; >> } >> >> +static bool ex_handler_uaccess_type(const struct exception_table_entry *ex, >> + struct pt_regs *regs, >> + unsigned long fixup_type) >> +{ >> + regs->regs[16] = fixup_type; >> + return ex_handler_fixup(ex, regs); >> +} >> + >> static bool ex_handler_uaccess_err_zero(const struct exception_table_entry *ex, >> struct pt_regs *regs) >> { >> @@ -75,6 +83,8 @@ bool fixup_exception(struct pt_regs *regs) >> switch (ex->type) { >> case EX_TYPE_FIXUP: >> return ex_handler_fixup(ex, regs); >> + case EX_TYPE_UACCESS_MC: >> + return ex_handler_uaccess_type(ex, regs, FIXUP_TYPE_NORMAL); >> case EX_TYPE_BPF: >> return ex_handler_bpf(ex, regs); >> case EX_TYPE_UACCESS_ERR_ZERO: >> @@ -94,10 +104,10 @@ bool fixup_exception_mc(struct pt_regs *regs) >> if (!ex) >> return false; >> >> - /* >> - * This is not complete, More Machine check safe extable type can >> - * be processed here. >> - */ >> + switch (ex->type) { >> + case EX_TYPE_UACCESS_MC: >> + return ex_handler_uaccess_type(ex, regs, FIXUP_TYPE_MC); >> + } >> >> return false; >> } >> -- >> 2.25.1 >> > .