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[2003:ea:8f04:7c00:5d9c:1ca4:a630:705f]) by smtp.googlemail.com with ESMTPSA id w125sm29866191wmg.32.2019.09.01.23.07.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 01 Sep 2019 23:07:07 -0700 (PDT) Subject: Re: [PATCH net-next 3/3] net: phy: realtek: add support for the 2.5Gbps PHY in RTL8125 To: Florian Fainelli , Andrew Lunn Cc: David Miller , "netdev@vger.kernel.org" References: <64769c3d-42b6-8eb8-26e4-722869408986@gmail.com> <20190808193743.GL27917@lunn.ch> <20190808202029.GN27917@lunn.ch> <94cc3fe3-98ed-d8d2-2444-84bf3eae0c5e@gmail.com> From: Heiner Kallweit Message-ID: Date: Mon, 2 Sep 2019 08:07:01 +0200 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org On 02.09.2019 04:07, Florian Fainelli wrote: > > > On 8/8/2019 1:24 PM, Heiner Kallweit wrote: >> On 08.08.2019 22:20, Andrew Lunn wrote: >>>> I have a contact in Realtek who provided the information about >>>> the vendor-specific registers used in the patch. I also asked for >>>> a method to auto-detect 2.5Gbps support but have no feedback so far. >>>> What may contribute to the problem is that also the integrated 1Gbps >>>> PHY's (all with the same PHY ID) differ significantly from each other, >>>> depending on the network chip version. >>> >>> Hi Heiner >>> >>> Some of the PHYs embedded in Marvell switches have an OUI, but no >>> product ID. We work around this brokenness by trapping the reads to >>> the ID registers in the MDIO bus controller driver and inserting the >>> switch product ID. The Marvell PHY driver then recognises these IDs >>> and does the right thing. >>> >>> Maybe you can do something similar here? >>> >> Yes, this would be an idea. Let me check. > > Since this is an integrated PHY you could have the MAC driver pass a > specific phydev->dev_flag bit that indicates that this is RTL8215, since > I am assuming that PCI IDs for those different chipsets do have to be > allocated, right? > Hi Florian, thanks for the feedback. In the meantime Realtek provided a method to identify NBaseT-capable PHY's, and the respective match_phy_device callback implementations had been done in 5181b473d64e ("net: phy: realtek: add NBase-T PHY auto-detection"). Heiner