diff for duplicates of <a3da0d24e6749b054f8a65656ec40d4aa0b9f2dc.camel@mediatek.com> diff --git a/N1/2.bin b/N1/2.bin new file mode 100644 index 0000000..00d2074 --- /dev/null +++ b/N1/2.bin @@ -0,0 +1,175 @@ +<html><body><p> +<pre> +Hi, Jason: + +On Thu, 2024-09-26 at 16:35 +0800, Jason-JH.Lin wrote: +> OVL_CON_CLRFMT_MAN is a configuration for extending color format +> settings of DISP_REG_OVL_CON(n). +> It will change some of the original color format settings. +>  +> Take the settings of (3 << 12) for example. +> - If OVL_CON_CLRFMT_MAN = 0 means OVL_CON_CLRFMT_RGBA8888. +> - If OVL_CON_CLRFMT_MAN = 1 means OVL_CON_CLRFMT_PARGB8888. +>  +> Since previous SoCs did not support OVL_CON_CLRFMT_MAN, this means +> that the SoC does not support the premultiplied color format. +> It will break the original color format setting of MT8173. +>  +> Therefore, the blend_modes is added to the driver data and then +> mtk_ovl_fmt_convert() will check the blend_modes to see if +> premultiplied supported in current platform. +> If it is not supported, use coverage mode to set it to the supported +> color formats to solve the degradation problem. +>  +> Fixes: a3f7f7ef4bfe ("drm/mediatek: Support "Pre-multiplied" blending in OVL") +> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com> +> Tested-by: Alper Nebi Yasak <alpernebiyasak@gmail.com> +> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +This version has difference over 50% with previous version. +It's better to drop these tested-by and reviewed-by tag. + +> --- +>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 41 ++++++++++++++++++++----- +>  1 file changed, 34 insertions(+), 7 deletions(-) +>  +> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +> index 89b439dcf3a6..0cf7b80f612e 100644 +> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c +> @@ -146,6 +146,7 @@ struct mtk_disp_ovl_data { +>  bool fmt_rgb565_is_0; +>  bool smi_id_en; +>  bool supports_afbc; +> +const u32 blend_modes; +>  const u32 *formats; +>  size_t num_formats; +>  bool supports_clrfmt_ext; +> @@ -386,14 +387,23 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int idx, +>        DISP_REG_OVL_RDMA_CTRL(idx)); +>  } +>   +> -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt, +> -    unsigned int blend_mode) +> +static unsigned int mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl, +> +struct mtk_plane_state *state) +>  { +> -/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" +> - * is defined in mediatek HW data sheet. +> - * The alphabet order in XXX is no relation to data +> - * arrangement in memory. + +I don't know why you drop these comment. +Without this modification, + +Reviewed-by: CK Hu <ck.hu@mediatek.com> + +> +unsigned int fmt = state->pending.format; +> +unsigned int blend_mode = state->base.pixel_blend_mode; +> + +> +/* +> + * For the platforms where OVL_CON_CLRFMT_MAN is defined in the hardware data sheet +> + * and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB8888. +> + * +> + * Check blend_modes in the driver data to see if premultiplied mode is supported. +> + * If not, use coverage mode instead to set it to the supported color formats. +>   */ +> +if (!(ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) && +> +    blend_mode == DRM_MODE_BLEND_PREMULTI) +> +blend_mode = DRM_MODE_BLEND_COVERAGE; +> + +>  switch (fmt) { +>  default: +>  case DRM_FORMAT_RGB565: +> @@ -471,7 +481,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx, +>  return; +>  } +>   +> -con = ovl_fmt_convert(ovl, fmt, blend_mode); +> +con = mtk_ovl_fmt_convert(ovl, state); +>  if (state->base.fb) { +>  con |= OVL_CON_AEN; +>  con |= state->base.alpha & OVL_CON_ALPHA; +> @@ -626,6 +636,8 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { +>  .gmc_bits = 8, +>  .layer_nr = 4, +>  .fmt_rgb565_is_0 = false, +> +.blend_modes = BIT(DRM_MODE_BLEND_COVERAGE) | +> +       BIT(DRM_MODE_BLEND_PIXEL_NONE), +>  .formats = mt8173_formats, +>  .num_formats = ARRAY_SIZE(mt8173_formats), +>  }; +> @@ -635,6 +647,8 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { +>  .gmc_bits = 8, +>  .layer_nr = 4, +>  .fmt_rgb565_is_0 = true, +> +.blend_modes = BIT(DRM_MODE_BLEND_COVERAGE) | +> +       BIT(DRM_MODE_BLEND_PIXEL_NONE), +>  .formats = mt8173_formats, +>  .num_formats = ARRAY_SIZE(mt8173_formats), +>  }; +> @@ -644,6 +658,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = { +>  .gmc_bits = 10, +>  .layer_nr = 4, +>  .fmt_rgb565_is_0 = true, +> +.blend_modes = BIT(DRM_MODE_BLEND_COVERAGE) | +> +       BIT(DRM_MODE_BLEND_PIXEL_NONE), +>  .formats = mt8173_formats, +>  .num_formats = ARRAY_SIZE(mt8173_formats), +>  }; +> @@ -653,6 +669,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = { +>  .gmc_bits = 10, +>  .layer_nr = 2, +>  .fmt_rgb565_is_0 = true, +> +.blend_modes = BIT(DRM_MODE_BLEND_COVERAGE) | +> +       BIT(DRM_MODE_BLEND_PIXEL_NONE), +>  .formats = mt8173_formats, +>  .num_formats = ARRAY_SIZE(mt8173_formats), +>  }; +> @@ -663,6 +681,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = { +>  .layer_nr = 4, +>  .fmt_rgb565_is_0 = true, +>  .smi_id_en = true, +> +.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) | +> +       BIT(DRM_MODE_BLEND_COVERAGE) | +> +       BIT(DRM_MODE_BLEND_PIXEL_NONE), +>  .formats = mt8173_formats, +>  .num_formats = ARRAY_SIZE(mt8173_formats), +>  }; +> @@ -673,6 +694,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = { +>  .layer_nr = 2, +>  .fmt_rgb565_is_0 = true, +>  .smi_id_en = true, +> +.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) | +> +       BIT(DRM_MODE_BLEND_COVERAGE) | +> +       BIT(DRM_MODE_BLEND_PIXEL_NONE), +>  .formats = mt8173_formats, +>  .num_formats = ARRAY_SIZE(mt8173_formats), +>  }; +> @@ -684,6 +708,9 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = { +>  .fmt_rgb565_is_0 = true, +>  .smi_id_en = true, +>  .supports_afbc = true, +> +.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) | +> +       BIT(DRM_MODE_BLEND_COVERAGE) | +> +       BIT(DRM_MODE_BLEND_PIXEL_NONE), +>  .formats = mt8195_formats, +>  .num_formats = ARRAY_SIZE(mt8195_formats), +>  .supports_clrfmt_ext = true, + +</pre> +</p></body></html><!--type:text--><!--{--><pre>************* MEDIATEK Confidentiality Notice + ******************** +The information contained in this e-mail message (including any +attachments) may be confidential, proprietary, privileged, or otherwise +exempt from disclosure under applicable laws. It is intended to be +conveyed only to the designated recipient(s). Any use, dissemination, +distribution, printing, retaining or copying of this e-mail (including its +attachments) by unintended recipient(s) is strictly prohibited and may +be unlawful. If you are not an intended recipient of this e-mail, or believe + +that you have received this e-mail in error, please notify the sender +immediately (by replying to this e-mail), delete any and all copies of +this e-mail (including any attachments) from your system, and do not +disclose the content of this e-mail to any other person. Thank you! +</pre><!--}--> diff --git a/N1/2.hdr b/N1/2.hdr new file mode 100644 index 0000000..da1f671 --- /dev/null +++ b/N1/2.hdr @@ -0,0 +1,3 @@ +Content-Type: text/html; + charset="utf-8" +Content-Transfer-Encoding: base64 diff --git a/a/content_digest b/N1/content_digest index 0a145bd..b891457 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -15,7 +15,7 @@ dri-devel@lists.freedesktop.org <dri-devel@lists.freedesktop.org> Project_Global_Chrome_Upstream_Group <Project_Global_Chrome_Upstream_Group@mediatek.com> " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0" - "\00:1\0" + "\01:1\0" "b\0" "Hi, Jason:\n" "\n" @@ -173,5 +173,182 @@ "> \t.formats = mt8195_formats,\n" "> \t.num_formats = ARRAY_SIZE(mt8195_formats),\n" "> \t.supports_clrfmt_ext = true," + "\01:2\0" + "b\0" + "<html><body><p>\r\n" + "<pre>\r\n" + "Hi, Jason:\r\n" + "\r\n" + "On Thu, 2024-09-26 at 16:35 +0800, Jason-JH.Lin wrote:\r\n" + "> OVL_CON_CLRFMT_MAN is a configuration for extending color format\r\n" + "> settings of DISP_REG_OVL_CON(n).\r\n" + "> It will change some of the original color format settings.\r\n" + "> \r\n" + "> Take the settings of (3 << 12) for example.\r\n" + "> - If OVL_CON_CLRFMT_MAN = 0 means OVL_CON_CLRFMT_RGBA8888.\r\n" + "> - If OVL_CON_CLRFMT_MAN = 1 means OVL_CON_CLRFMT_PARGB8888.\r\n" + "> \r\n" + "> Since previous SoCs did not support OVL_CON_CLRFMT_MAN, this means\r\n" + "> that the SoC does not support the premultiplied color format.\r\n" + "> It will break the original color format setting of MT8173.\r\n" + "> \r\n" + "> Therefore, the blend_modes is added to the driver data and then\r\n" + "> mtk_ovl_fmt_convert() will check the blend_modes to see if\r\n" + "> premultiplied supported in current platform.\r\n" + "> If it is not supported, use coverage mode to set it to the supported\r\n" + "> color formats to solve the degradation problem.\r\n" + "> \r\n" + "> Fixes: a3f7f7ef4bfe ("drm/mediatek: Support "Pre-multiplied" blending in OVL")\r\n" + "> Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>\r\n" + "> Tested-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>\r\n" + "> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>\r\n" + "\r\n" + "This version has difference over 50% with previous version.\r\n" + "It's better to drop these tested-by and reviewed-by tag.\r\n" + "\r\n" + "> ---\r\n" + ">  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 41 ++++++++++++++++++++-----\r\n" + ">  1 file changed, 34 insertions(+), 7 deletions(-)\r\n" + "> \r\n" + "> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c\r\n" + "> index 89b439dcf3a6..0cf7b80f612e 100644\r\n" + "> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c\r\n" + "> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c\r\n" + "> @@ -146,6 +146,7 @@ struct mtk_disp_ovl_data {\r\n" + ">  bool fmt_rgb565_is_0;\r\n" + ">  bool smi_id_en;\r\n" + ">  bool supports_afbc;\r\n" + "> +const u32 blend_modes;\r\n" + ">  const u32 *formats;\r\n" + ">  size_t num_formats;\r\n" + ">  bool supports_clrfmt_ext;\r\n" + "> @@ -386,14 +387,23 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int idx,\r\n" + ">        DISP_REG_OVL_RDMA_CTRL(idx));\r\n" + ">  }\r\n" + ">  \r\n" + "> -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt,\r\n" + "> -    unsigned int blend_mode)\r\n" + "> +static unsigned int mtk_ovl_fmt_convert(struct mtk_disp_ovl *ovl,\r\n" + "> +struct mtk_plane_state *state)\r\n" + ">  {\r\n" + "> -/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"\r\n" + "> - * is defined in mediatek HW data sheet.\r\n" + "> - * The alphabet order in XXX is no relation to data\r\n" + "> - * arrangement in memory.\r\n" + "\r\n" + "I don't know why you drop these comment.\r\n" + "Without this modification,\r\n" + "\r\n" + "Reviewed-by: CK Hu <ck.hu@mediatek.com>\r\n" + "\r\n" + "> +unsigned int fmt = state->pending.format;\r\n" + "> +unsigned int blend_mode = state->base.pixel_blend_mode;\r\n" + "> +\r\n" + "> +/*\r\n" + "> + * For the platforms where OVL_CON_CLRFMT_MAN is defined in the hardware data sheet\r\n" + "> + * and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB8888.\r\n" + "> + *\r\n" + "> + * Check blend_modes in the driver data to see if premultiplied mode is supported.\r\n" + "> + * If not, use coverage mode instead to set it to the supported color formats.\r\n" + ">   */\r\n" + "> +if (!(ovl->data->blend_modes & BIT(DRM_MODE_BLEND_PREMULTI)) &&\r\n" + "> +    blend_mode == DRM_MODE_BLEND_PREMULTI)\r\n" + "> +blend_mode = DRM_MODE_BLEND_COVERAGE;\r\n" + "> +\r\n" + ">  switch (fmt) {\r\n" + ">  default:\r\n" + ">  case DRM_FORMAT_RGB565:\r\n" + "> @@ -471,7 +481,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,\r\n" + ">  return;\r\n" + ">  }\r\n" + ">  \r\n" + "> -con = ovl_fmt_convert(ovl, fmt, blend_mode);\r\n" + "> +con = mtk_ovl_fmt_convert(ovl, state);\r\n" + ">  if (state->base.fb) {\r\n" + ">  con |= OVL_CON_AEN;\r\n" + ">  con |= state->base.alpha & OVL_CON_ALPHA;\r\n" + "> @@ -626,6 +636,8 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {\r\n" + ">  .gmc_bits = 8,\r\n" + ">  .layer_nr = 4,\r\n" + ">  .fmt_rgb565_is_0 = false,\r\n" + "> +.blend_modes = BIT(DRM_MODE_BLEND_COVERAGE) |\r\n" + "> +       BIT(DRM_MODE_BLEND_PIXEL_NONE),\r\n" + ">  .formats = mt8173_formats,\r\n" + ">  .num_formats = ARRAY_SIZE(mt8173_formats),\r\n" + ">  };\r\n" + "> @@ -635,6 +647,8 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {\r\n" + ">  .gmc_bits = 8,\r\n" + ">  .layer_nr = 4,\r\n" + ">  .fmt_rgb565_is_0 = true,\r\n" + "> +.blend_modes = BIT(DRM_MODE_BLEND_COVERAGE) |\r\n" + "> +       BIT(DRM_MODE_BLEND_PIXEL_NONE),\r\n" + ">  .formats = mt8173_formats,\r\n" + ">  .num_formats = ARRAY_SIZE(mt8173_formats),\r\n" + ">  };\r\n" + "> @@ -644,6 +658,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {\r\n" + ">  .gmc_bits = 10,\r\n" + ">  .layer_nr = 4,\r\n" + ">  .fmt_rgb565_is_0 = true,\r\n" + "> +.blend_modes = BIT(DRM_MODE_BLEND_COVERAGE) |\r\n" + "> +       BIT(DRM_MODE_BLEND_PIXEL_NONE),\r\n" + ">  .formats = mt8173_formats,\r\n" + ">  .num_formats = ARRAY_SIZE(mt8173_formats),\r\n" + ">  };\r\n" + "> @@ -653,6 +669,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {\r\n" + ">  .gmc_bits = 10,\r\n" + ">  .layer_nr = 2,\r\n" + ">  .fmt_rgb565_is_0 = true,\r\n" + "> +.blend_modes = BIT(DRM_MODE_BLEND_COVERAGE) |\r\n" + "> +       BIT(DRM_MODE_BLEND_PIXEL_NONE),\r\n" + ">  .formats = mt8173_formats,\r\n" + ">  .num_formats = ARRAY_SIZE(mt8173_formats),\r\n" + ">  };\r\n" + "> @@ -663,6 +681,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {\r\n" + ">  .layer_nr = 4,\r\n" + ">  .fmt_rgb565_is_0 = true,\r\n" + ">  .smi_id_en = true,\r\n" + "> +.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |\r\n" + "> +       BIT(DRM_MODE_BLEND_COVERAGE) |\r\n" + "> +       BIT(DRM_MODE_BLEND_PIXEL_NONE),\r\n" + ">  .formats = mt8173_formats,\r\n" + ">  .num_formats = ARRAY_SIZE(mt8173_formats),\r\n" + ">  };\r\n" + "> @@ -673,6 +694,9 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {\r\n" + ">  .layer_nr = 2,\r\n" + ">  .fmt_rgb565_is_0 = true,\r\n" + ">  .smi_id_en = true,\r\n" + "> +.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |\r\n" + "> +       BIT(DRM_MODE_BLEND_COVERAGE) |\r\n" + "> +       BIT(DRM_MODE_BLEND_PIXEL_NONE),\r\n" + ">  .formats = mt8173_formats,\r\n" + ">  .num_formats = ARRAY_SIZE(mt8173_formats),\r\n" + ">  };\r\n" + "> @@ -684,6 +708,9 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {\r\n" + ">  .fmt_rgb565_is_0 = true,\r\n" + ">  .smi_id_en = true,\r\n" + ">  .supports_afbc = true,\r\n" + "> +.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |\r\n" + "> +       BIT(DRM_MODE_BLEND_COVERAGE) |\r\n" + "> +       BIT(DRM_MODE_BLEND_PIXEL_NONE),\r\n" + ">  .formats = mt8195_formats,\r\n" + ">  .num_formats = ARRAY_SIZE(mt8195_formats),\r\n" + ">  .supports_clrfmt_ext = true,\r\n" + "\r\n" + "</pre>\r\n" + "</p></body></html><!--type:text--><!--{--><pre>************* MEDIATEK Confidentiality Notice\r\n" + " ********************\r\n" + "The information contained in this e-mail message (including any \r\n" + "attachments) may be confidential, proprietary, privileged, or otherwise\r\n" + "exempt from disclosure under applicable laws. It is intended to be \r\n" + "conveyed only to the designated recipient(s). Any use, dissemination, \r\n" + "distribution, printing, retaining or copying of this e-mail (including its \r\n" + "attachments) by unintended recipient(s) is strictly prohibited and may \r\n" + "be unlawful. If you are not an intended recipient of this e-mail, or believe\r\n" + " \r\n" + "that you have received this e-mail in error, please notify the sender \r\n" + "immediately (by replying to this e-mail), delete any and all copies of \r\n" + "this e-mail (including any attachments) from your system, and do not\r\n" + "disclose the content of this e-mail to any other person. Thank you!\r\n" + </pre><!--}--> -8861cadab3403e670ddceddb3463f5a176d82116f53fa38a5f4cea740a36cf36 +7089edf82e9768e84eec715ebabcab8b513dc0710120513419b24a9866c19fd4
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