From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80038C07E94 for ; Fri, 4 Jun 2021 09:01:53 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4415C613BF for ; Fri, 4 Jun 2021 09:01:53 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4415C613BF Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=intel-gfx-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B24296F5DF; Fri, 4 Jun 2021 09:01:48 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 05BCB6F5DA; Fri, 4 Jun 2021 09:01:46 +0000 (UTC) IronPort-SDR: n9KeJr1ysiayJUKszTnxtM3F9Aoe74JvBnyhis3e0+e14Bs3voyDyQ4xDhE0d4yxEvEwiheZaq HnRJHgIqv+VA== X-IronPort-AV: E=McAfee;i="6200,9189,10004"; a="191362613" X-IronPort-AV: E=Sophos;i="5.83,247,1616482800"; d="scan'208";a="191362613" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 02:01:44 -0700 IronPort-SDR: 9G3b3ztjFYHK+ovsfibgfE3FQUGBWpuV8Qn4Nq+ppjbmCm0m2C5xR5Lpr+v6kzd1MlcovVl3b/ 8yXJdgDKIVyQ== X-IronPort-AV: E=Sophos;i="5.83,247,1616482800"; d="scan'208";a="618201600" Received: from janlundk-mobl1.ger.corp.intel.com (HELO [10.249.254.183]) ([10.249.254.183]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 02:01:42 -0700 To: =?UTF-8?Q?Christian_K=c3=b6nig?= , Daniel Vetter , Maarten Lankhorst References: <68e6057c-df17-64ce-3116-cd5e79578795@amd.com> From: =?UTF-8?Q?Thomas_Hellstr=c3=b6m?= Message-ID: Date: Fri, 4 Jun 2021 11:01:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <68e6057c-df17-64ce-3116-cd5e79578795@amd.com> Content-Language: en-US Subject: Re: [Intel-gfx] Merging TTM branches through the Intel tree? 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mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73C59C07E94 for ; Fri, 4 Jun 2021 09:01:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 33A35613AC for ; Fri, 4 Jun 2021 09:01:49 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 33A35613AC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 293B36F5DA; Fri, 4 Jun 2021 09:01:48 +0000 (UTC) Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 05BCB6F5DA; Fri, 4 Jun 2021 09:01:46 +0000 (UTC) IronPort-SDR: n9KeJr1ysiayJUKszTnxtM3F9Aoe74JvBnyhis3e0+e14Bs3voyDyQ4xDhE0d4yxEvEwiheZaq HnRJHgIqv+VA== X-IronPort-AV: E=McAfee;i="6200,9189,10004"; a="191362613" X-IronPort-AV: E=Sophos;i="5.83,247,1616482800"; d="scan'208";a="191362613" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 02:01:44 -0700 IronPort-SDR: 9G3b3ztjFYHK+ovsfibgfE3FQUGBWpuV8Qn4Nq+ppjbmCm0m2C5xR5Lpr+v6kzd1MlcovVl3b/ 8yXJdgDKIVyQ== X-IronPort-AV: E=Sophos;i="5.83,247,1616482800"; d="scan'208";a="618201600" Received: from janlundk-mobl1.ger.corp.intel.com (HELO [10.249.254.183]) ([10.249.254.183]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jun 2021 02:01:42 -0700 Subject: Re: [Intel-gfx] Merging TTM branches through the Intel tree? To: =?UTF-8?Q?Christian_K=c3=b6nig?= , Daniel Vetter , Maarten Lankhorst References: <68e6057c-df17-64ce-3116-cd5e79578795@amd.com> From: =?UTF-8?Q?Thomas_Hellstr=c3=b6m?= Message-ID: Date: Fri, 4 Jun 2021 11:01:40 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.10.1 MIME-Version: 1.0 In-Reply-To: <68e6057c-df17-64ce-3116-cd5e79578795@amd.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?Q?Thomas_Hellstr=c3=b6m_=28Intel=29?= , Intel Graphics Development , DRI Development , Matthew Auld Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 6/4/21 9:51 AM, Christian König wrote: > Am 03.06.21 um 09:36 schrieb Daniel Vetter: >> On Thu, Jun 3, 2021 at 8:50 AM Thomas Hellström >> wrote: >>> >>> On 6/2/21 8:40 PM, Daniel Vetter wrote: >>>> On Wed, Jun 02, 2021 at 11:48:41AM +0200, Christian König wrote: >>>>> Am 02.06.21 um 11:16 schrieb Thomas Hellström (Intel): >>>>>> On 6/2/21 10:32 AM, Christian König wrote: >>>>>>> Uff I'm just waiting for feedback from Philip to merge a large >>>>>>> patch >>>>>>> set for TTM through drm-misc-next. >>>>>>> >>>>>>> I'm pretty sure we will run into merge conflicts if you try to push >>>>>>> your changes through the Intel tree. >>>>>>> >>>>>>> Christian. >>>>>> OK, so what would be the best approach here?, Adding the TTM >>>>>> patches to >>>>>> drm-misc-next when your set has landed? >>>>> I think I will send out out my set to Matthew once more for >>>>> review, then >>>>> push the common TTM stuff to drm-misc-next as much as possible. >>>>> >>>>> Then you should be able to land your stuff to drm-misc-next and >>>>> rebase on >>>>> the end result. >>>>> >>>>> Just need to note to David that drm-misc-next should be merged to >>>>> drm-next >>>>> before the Intel patches depending on that stuff land as well. >>>> Other option (because the backmerges tend to be slow) is a topic >>>> branch, >>>> and we just eat/resolve the conflicts in both drm-misc-next and >>>> drm-intel-gt-next in the merge commit. If it's not too bad (I haven't >>>> looked at what exactly we need for the i915 side from ttm in detail). >>>> >>>> But also often figuring out the topic branch logistics takes longer >>>> than >>>> just merging to drm-misc-next as the patches get ready. >>>> -Daniel >>> Daniel: So the thing we need to get into TTM is the iterator-based >>> move_memcpy which is more adaptable than the current one and needed to >>> support non-linear lmem buffers, some bug-fixes and minor changes to be >>> able to keep our short-term-pinning while on the LRU. A necessary evil. >>> >>> Christian: it looks like you have landed some TTM changes already, in >>> particular the &bo->mem -> bo->resource change which is the main >>> conflict I think. > > Yes, I thought that pushing this with Matthew rb should solve at least > a bit of the conflict. > >>> Is the 10 patches self-allocation series the main >>> remaining part? > > Yes, exactly. I only need Matthew's, Daniel's or your ok and I'm good > to go as well > >>> That will probably cause some conflicts with already >>> pushed i915 TTM setup code, but otherwise will not conflict with the >>> rest of the TTM code I think, which should make it possible to bring in >>> our TTM changes after conflict resolution with what you've already >>> pushed. The memcpy code is pretty self-contained. >> I think in that case topic branch on top of drm-next (once the ttm >> bits we conflict with are there) is probably best, and then pull that >> into drm-misc-next and drm-intel-gt-next. Merge window freeze is also >> approach, so without topic branch we'd be stuck until like -rc2 when >> drm-next reopens. I guess Maarten can do the topic branch logistics in >> drm-misc.git for this. > > That approach sounds good to me as well. > > The amdgpu branch had some merge conflicts as well, but nothing we > couldn't fix. OK, so this is going to be a little tricky, I guess. From what I can tell, the memcpy TTM stuff is resolved locally and can be merged to drm-misc-next immediately. It might have a very minor conflict with your 10 patches I think, if any. Your 10 patches will conflict slightly with current drm-intel-gt-next I think. Remaining intel patches will conflict only with current drm-misc-next. So We could have pull order - drm-misc-next up to bot not including your 10 patches, - drm-intel-gt-next - drm-misc-next from your 10 paches and onwards, - Intel's ttm enablement topic branch. Whether I push the ttm memcpy stuff before your 10 patches or after shouldn't really matter except it might take some time to resolve the 10 patches - drm-intel-gt-next conflict in drm-tip. So OK to merge the memcpy stuff to drm-misc-next now or do you want me to hold on? I'll take a look at what's remaining to review in your series. I guess it's in our interest that both these series get merged asap. /Thomas > > Christian. > >> -Daniel >