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Wed, 11 Mar 2026 05:42:59 -0700 (PDT) Message-ID: Date: Wed, 11 Mar 2026 14:42:57 +0200 Precedence: bulk X-Mailing-List: linux-clk@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 00/15] PCI: renesas: Add RZ/G3E PCIe controller support To: John Madieu , claudiu.beznea.uj@bp.renesas.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, geert+renesas@glider.be, krzk+dt@kernel.org Cc: robh@kernel.org, bhelgaas@google.com, conor+dt@kernel.org, magnus.damm@gmail.com, biju.das.jz@bp.renesas.com, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, john.madieu@gmail.com References: <20260306143423.19562-1-john.madieu.xa@bp.renesas.com> Content-Language: en-US From: Claudiu Beznea In-Reply-To: <20260306143423.19562-1-john.madieu.xa@bp.renesas.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 3/6/26 16:34, John Madieu wrote: > The Renesas RZ/G3E SoC features a PCIe controller that shares similarities with > the existing RZ/G3S PCIe controller, but with several key differences. > This series adds support for the RZ/G3E PCIe controller by extending the existing > RZ/G3S driver and device tree bindings. > > Key differences between RZ/G3E and RZ/G3S PCIe controllers: > > Link Speed Support: > - RZ/G3E: Supports PCIe Gen3 (8.0 GT/s) alongside Gen2 (5.0 GT/s) > - RZ/G3S: Supports PCIe Gen2 (5.0 GT/s) only > > Reset Control: > - RZ/G3E: Uses register-based reset control mechanism > - RZ/G3S: Uses exclusively external reset control signals > > Inbound Window Configuration: > - RZ/G3E: Requires precise power-of-2 window coverage with strict address > alignment constraints. Non-power-of-2 memory regions must be split into > multiple windows to avoid over-mapping, ensuring proper hardware address > decoding for DMA operations. > - RZ/G3S: Uses a simpler approach that rounds up to the next power-of-2, > creating single larger windows. The hardware tolerates over-mapped regions. > > Class/Revision IDs: > - RZ/G3E: Requires explicit setting of class/revision values > - RZ/G3S: Has default values in hardware > > Clock Naming: > - RZ/G3E: Uses "clkpmu" clock for power management > - RZ/G3S: Uses "clkl1pm" PM control clock while CLKREQ_B is deasserting > > Phy Settings: > - RZ/G3E: Does not need PHY settings as it works with default hw values > - RZ/G3S: Requires explicit PHY settings > > This series extends the existing driver to detect the SoC type from the device > tree compatible string and configure the controller appropriately. The updates > are minimal and focused on the hardware-specific differences while keeping the > common code paths unified. > > Changes: > > v8: > - Collected additional Rb tags on remaining code patches > - Fixed typos in patch descriptions > - Fixed checkpatch warnings I've tested this series on Renesas RZ/G3S SMARC Carrier-II board with an NVMe device: root@smarc-rzg3s:/lava-testing# lspci 00:00.0 PCI bridge: Renesas Technology Corp. Device 0033 01:00.0 Non-Volatile memory controller: Transcend Information, Inc. NVMe PCIe SSD 110S/112S/120S/MTE300S/MTE400S/MTE652T2 (DRAM-less) (rev 03) root@smarc-rzg3s:/lava-testing# All looks good, thus, for all the patches in this series: Tested-by: Claudiu Beznea Thank you, Claudiu