RE: [PATCH v4 1/4] mtd: spi-nor-ids: Add XMC XM25QH128C

[<Takahiro.Kuwano@infineon.com>]

Hi,

> From: Fabio Estevam <festevam@nabladev.com>
> 
> Add the JEDEC ID for the XMC XM25QH128C SPI NOR flash.
> 
> This is a 128Mbit device using 64KiB sectors and supporting 4KiB
> erase, dual read and quad read, matching the other XM25QH128 variants.
> 
> Cc: Vignesh Raghavendra <vigneshr@ti.com>
> Cc: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
> Signed-off-by: Fabio Estevam <festevam@nabladev.com>
> ---

It would be nice to have Link: tag followed by datasheet URL [1].

> Changes since v3:
> - None.
> 
>  drivers/mtd/spi/spi-nor-ids.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index 31a2ba49a87c..90aa1025176c 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -673,6 +673,7 @@ const struct flash_info spi_nor_ids[] = {
>         { INFO("XM25QH64A", 0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("XM25QH64C", 0x204017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("XM25QH128A", 0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> +       { INFO("XM25QH128C", 0x204018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

Per the datasheet, this chip supports Dual/Quad ops but for my reference,
could you let me know if you tested 1-1-4 or 1-4-4 ops? 

Anyway,
Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>

>         { INFO("XM25QU128C", 0x204118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
>         { INFO("XM25QH256C", 0x204019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_4B_OPCODES) },
>         { INFO("XM25QU256C", 0x204119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> SPI_NOR_4B_OPCODES) },
> --
> 2.43.0

[1] https://www.xmcwh.com/uploads/435/XM25QH128C.pdf