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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49cf772692dsm70648315e9.10.2026.09.04.03.42.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Sep 2026 03:42:46 -0700 (PDT) Message-ID: Date: Fri, 4 Sep 2026 12:42:45 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 14/16] hw/riscv: Add property to hart array to allow private memory Content-Language: en-US To: Joel Stanley , Alistair Francis , Daniel Henrique Barboza Cc: Portia Stephens , Weiwei Li , Liu Zhiwei , Chao Liu , Nicholas Piggin , Anirudh Srinivasan , Michael Ellerman , =?UTF-8?Q?C=C3=A9dric_Le_Goater?= , qemu-riscv@nongnu.org, qemu-devel@nongnu.org References: <20260903055131.257903-1-joel@jms.id.au> <20260903055131.257903-15-joel@jms.id.au> From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20260903055131.257903-15-joel@jms.id.au> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTA0MDA5NiBTYWx0ZWRfX+I4I8R0SHK3z hqhlzM6L2stK4vA8DDIBW8OzYXSu/2U7nFC90GN0hgOGYtv0YMu5/0HzoID5pEMhNop8usCHkXU qmxE0f3yq1gTrOpV3wc7cl9YVdxyNcg= X-Proofpoint-ORIG-GUID: j1xBtSpNlzDk61fUE3-htdrQKTe2HNtj X-Proofpoint-GUID: j1xBtSpNlzDk61fUE3-htdrQKTe2HNtj X-Authority-Analysis: v=2.4 cv=T/S8ifKQ c=1 sm=1 tr=0 ts=6a9aa0a8 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=4s3hRJSeHn4rkQlkrse1kQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=t9496tuAAAAA:8 a=EUspDBNiAAAA:8 a=JF9118EUAAAA:8 a=S4Sp4hC2xgBoH1LN8d0A:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 a=4wQ91nGE5lQcD7eh5OX0:22 a=xVlTc564ipvMDusKsbsT:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTA0MDA5NiBTYWx0ZWRfX7rVVX6KR8Qnn UW85QUXpG4TVf+X4NHs+1NRQG0zFbN8XyIbnWX+UJvujiQeXqWHeyTSi87w700BzyA4ZFylxe6o PX1aWMkzocvT2l47tBM29AlP9FMCXJ5yzP9Hk2EwNRRV3tC2P/hbV07Ab9S8BaHOMvOQX2sZfRO YG55uhw7g7AbdtWm3+v7bn4yhpBDrUAUgxzhCgNFXpdbCgzR8yfNNzuwosHzDe1FM5rs/RMzjyz grNocgUB3qOG/H5T7ixUdW8sV/KPH5SwA94i1YY97KZC4pb+4BcRrwzivQM4ASJvhLfruX1EiKW GMvVGN+ijJs4JFD+y1tXo6xfyS4azKzdhQfcIw51/1fYbepZ/h1V14lyWl5KlbG8uupHuXN/SuZ V4ZfzhiMrWfTqwCoi0ACzIMaJSSY4wGbyaazGqTRyCxQ8Z48NAo1kepuzPwDrSzxEdfkA4OUOK7 YEO+0iZUg+lNICAxniQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-04_03,2026-09-03_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 clxscore=1015 spamscore=0 suspectscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2609040096 Received-SPF: pass client-ip=205.220.180.131; envelope-from=philmd@oss.qualcomm.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/9/26 07:51, Joel Stanley wrote: > From: Portia Stephens > > There are platforms where CPUs have different mapping of system memory. > The global system memory does not allow for this. This adds an optional > property on the hart array to assign a specific memory region. The array > passes the region to each hart it creates, so a machine can alias the > harts' memory to system memory, while the harts view memory from their > own memory region. > > Signed-off-by: Portia Stephens > Reviewed-by: Daniel Henrique Barboza > Reviewed-by: Alistair Francis > Signed-off-by: Joel Stanley > --- > include/hw/riscv/riscv_hart.h | 2 ++ > hw/riscv/riscv_hart.c | 8 ++++++++ > 2 files changed, 10 insertions(+) > > diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h > index 197fa1623115..c3cd05a2c877 100644 > --- a/include/hw/riscv/riscv_hart.h > +++ b/include/hw/riscv/riscv_hart.h > @@ -42,6 +42,8 @@ struct RISCVHartArrayState { > uint64_t *rnmi_irqvec; > uint32_t num_rnmi_excpvec; > uint64_t *rnmi_excpvec; > + /* Optional private memory region for use instead of system memory */ > + MemoryRegion *memory; > RISCVCPU *harts; > }; > > diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c > index 747754be6158..32fd39737ff6 100644 > --- a/hw/riscv/riscv_hart.c > +++ b/hw/riscv/riscv_hart.c > @@ -53,6 +53,8 @@ static const Property riscv_harts_props[] = { > DEFINE_PROP_ARRAY("rnmi-exception-vector", RISCVHartArrayState, > num_rnmi_excpvec, rnmi_excpvec, qdev_prop_uint64, > uint64_t), > + DEFINE_PROP_LINK("memory", RISCVHartArrayState, memory, > + TYPE_MEMORY_REGION, MemoryRegion *), > }; > > static void riscv_harts_cpu_reset(void *opaque) > @@ -117,6 +119,12 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, > object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type); > qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); > > + /* Use private memory instead of system_memory if provided */ > + if (s->memory) { > + object_property_set_link(OBJECT(&s->harts[idx]), "memory", > + OBJECT(s->memory), &error_abort); IMHO this logic should be inverted: we want explicit memory bus mapping by default, and if not set then take the global memory. Personally I'd even go further and assert it is set (otherwise programming error), with a preliminary patch setting global system memory to current machines. > + } > + > if (s->harts[idx].cfg.ext_smrnmi) { > if (idx < s->num_rnmi_irqvec) { > qdev_prop_set_uint64(DEVICE(&s->harts[idx]),