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Fri, 28 Nov 2025 03:32:47 -0800 (PST) Received: from [192.168.68.110] ([179.133.97.212]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-be508a1142esm4332414a12.19.2025.11.28.03.32.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Nov 2025 03:32:47 -0800 (PST) Message-ID: Date: Fri, 28 Nov 2025 08:32:42 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] target/riscv: Add "debug-1.0" to specify debug specification v1.0 To: Alvin Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: alistair.francis@wdc.com, bin.meng@windriver.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, vivahavey@gmail.com, Yu-Ming Chang References: <20251126164329.2157287-1-alvinga@andestech.com> <20251126164329.2157287-2-alvinga@andestech.com> From: Daniel Henrique Barboza Content-Language: en-US In-Reply-To: <20251126164329.2157287-2-alvinga@andestech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/26/25 1:43 PM, Alvin Chang wrote: > Currently RISC-V CPU has a property "debug" which is equivalent to old > debug specification v0.13 version. Now we have ratified debug > specification v1.0 version. To support both versions, we add "debug-1.0" > as one of RISC-V CPU property to let user specify that debug v0.13 or > debug v1.0 is enabled. When debug-1.0=false CPU fallbacks to default > v0.13 version. > > Note that "debug-1.0" depends on "debug" property: > - debug=false,debug-1.0={true|false} --> debug is disabled > - debug=true,debug-1.0=false --> debug v0.13 is enabled > - debug=true,debug-1.0=true --> debug v1.0 is enabled It is worth noticing that 'debug' is default true, so setting debug-1.0=true alone is enough to enable debug v1.0. If a new version becomes necessary we can add this clarification in the commit msg. Reviewed-by: Daniel Henrique Barboza > > Signed-off-by: Alvin Chang > Reviewed-by: Yu-Ming Chang > --- > target/riscv/cpu.c | 1 + > target/riscv/cpu_cfg_fields.h.inc | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 73d4280..082035b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -2637,6 +2637,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { > > static const Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), > + DEFINE_PROP_BOOL("debug-1.0", RISCVCPU, cfg.debug_1_00, false), > > {.name = "pmu-mask", .info = &prop_pmu_mask}, > {.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */ > diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc > index a154ecd..402b255 100644 > --- a/target/riscv/cpu_cfg_fields.h.inc > +++ b/target/riscv/cpu_cfg_fields.h.inc > @@ -151,6 +151,7 @@ BOOL_FIELD(ext_XVentanaCondOps) > BOOL_FIELD(mmu) > BOOL_FIELD(pmp) > BOOL_FIELD(debug) > +BOOL_FIELD(debug_1_00) > BOOL_FIELD(misa_w) > > BOOL_FIELD(short_isa_string)