Re: [PATCH u-boot 4/8] ufs: add CONFIG_UFS_RESTRICT_TX_LANES

[Neil Armstrong <neil.armstrong@linaro.org>]

On 10/4/26 21:22, Petr Hodina via B4 Relay wrote:
> From: Petr Hodina <petr.hodina@protonmail.com>
> 
> Add CONFIG_UFS_RESTRICT_TX_LANES, to restrict the amount
> PA_AVAILTXDATALANES = 1 at the start of ufshcd_link_startup().
> 
> Some platforms (notably the Sony Yoshino/Tama families on MSM8998 /
> SDM845) have only a single reliably-usable UFS TX lane.

Why can't this be a quirk set only on those platforms ?

Neil>
> Signed-off-by: Petr Hodina <petr.hodina@protonmail.com>
> ---
>   drivers/ufs/Kconfig      | 14 ++++++++++++++
>   drivers/ufs/ufs-uclass.c | 13 +++++++++++++
>   2 files changed, 27 insertions(+)
> 
> diff --git a/drivers/ufs/Kconfig b/drivers/ufs/Kconfig
> index 49472933de3..266e7180152 100644
> --- a/drivers/ufs/Kconfig
> +++ b/drivers/ufs/Kconfig
> @@ -8,6 +8,20 @@ config UFS
>   	  This selects support for Universal Flash Subsystem (UFS).
>   	  Say Y here if you want UFS Support.
>   
> +config UFS_RESTRICT_TX_LANES
> +	bool "Restrict the number of UFS TX lanes to 1"
> +	depends on UFS
> +	default n
> +	help
> +	  Say Y here to restrict the number of UFS TX lanes to 1. This saves
> +	  power at the cost of write performance.
> +
> +	  This is useful (and on some devices required) for platforms such as
> +	  the Sony Yoshino/Tama families where only a single TX lane is
> +	  reliably usable.
> +
> +	  If unsure, say N.
> +
>   config UFS_AMD_VERSAL2
>   	bool "AMD Versal Gen 2 UFS controller platform driver"
>   	depends on UFS && ZYNQMP_FIRMWARE
> diff --git a/drivers/ufs/ufs-uclass.c b/drivers/ufs/ufs-uclass.c
> index fdf62a69c02..977ffebc21f 100644
> --- a/drivers/ufs/ufs-uclass.c
> +++ b/drivers/ufs/ufs-uclass.c
> @@ -508,6 +508,19 @@ static int ufshcd_link_startup(struct ufs_hba *hba)
>   	int ret;
>   	int retries = DME_LINKSTARTUP_RETRIES;
>   
> +	if (IS_ENABLED(CONFIG_UFS_RESTRICT_TX_LANES)) {
> +		/*
> +		 * Restrict the number of available TX lanes to 1. This saves
> +		 * power at the cost of write performance and is required on
> +		 * some platforms (e.g. Sony Yoshino/Tama) where only a single
> +		 * TX lane is reliably usable.
> +		 */
> +		ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES), 1);
> +		if (ret)
> +			dev_warn(hba->dev, "%s: failed to restrict TX lanes: %d\n",
> +				 __func__, ret);
> +	}
> +
>   	do {
>   		ret = ufshcd_ops_link_startup_notify(hba, PRE_CHANGE);
>   		if (ret)
>