Re: [RFC PATCH v2 41/45] irqchip/gic-v3: Prepare for FEAT_GICv3_NMI support

[Jinjie Ruan <ruanjinjie@huawei.com>]

The title "irqchip/gic-v3: Rename *nmi* to *pseudo_nmi*" will be more clear

otherwise LGTM
Reviewed-by: Jinjie Ruan <ruanjinjie@huawei.com>

在 2026/7/28 0:34, Vladimir Murzin 写道:
> From: Lorenzo Pieralisi <lpieralisi@kernel.org>
> 
> Support for FEAT_GICv3_NMI is coming. Currently, the terms "NMI" and
> "pseudo-NMI" are used interchangeably. Rename helper functions and
> variables related to pseudo-NMI to make the code paths clearer and
> more explicit.
> 
> Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
> Signed-off-by: Mark Brown <broonie@kernel.org>
> Signed-off-by: Ada Couprie Diaz <ada.coupriediaz@arm.com>
> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
> ---
>  drivers/irqchip/irq-gic-v3.c | 28 ++++++++++++++--------------
>  1 file changed, 14 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
> index 94c6a3f2b009..c75acd5f9e7f 100644
> --- a/drivers/irqchip/irq-gic-v3.c
> +++ b/drivers/irqchip/irq-gic-v3.c
> @@ -87,7 +87,7 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
>  #define GIC_LINE_NR	min(GICD_TYPER_SPIS(gic_data.rdists.gicd_typer), 1020U)
>  #define GIC_ESPI_NR	GICD_TYPER_ESPIS(gic_data.rdists.gicd_typer)
>  
> -static bool nmi_support_forbidden;
> +static bool pseudo_nmi_support_forbidden;
>  
>  /*
>   * There are 16 SGIs, though we only actually use 8 in Linux. The other 8 SGIs
> @@ -117,7 +117,7 @@ static bool nmi_support_forbidden;
>   * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
>   *   interrupt.
>   */
> -static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
> +static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmi);
>  
>  static u32 gic_get_pribits(void)
>  {
> @@ -185,7 +185,7 @@ static void __init gic_prio_init(void)
>  				pr_warn("Broken GIC integration, security disabled\n");
>  		} else {
>  			pr_warn("Broken GIC integration, pNMI forbidden\n");
> -			nmi_support_forbidden = true;
> +			pseudo_nmi_support_forbidden = true;
>  		}
>  	}
>  
> @@ -512,10 +512,10 @@ static void gic_unmask_irq(struct irq_data *d)
>  	gic_poke_irq(d, GICD_ISENABLER);
>  }
>  
> -static inline bool gic_supports_nmi(void)
> +static inline bool gic_supports_pseudo_nmi(void)
>  {
>  	return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
> -	       static_branch_likely(&supports_pseudo_nmis);
> +	       static_branch_likely(&supports_pseudo_nmi);
>  }
>  
>  static int gic_irq_set_irqchip_state(struct irq_data *d,
> @@ -598,7 +598,7 @@ static int gic_irq_nmi_setup(struct irq_data *d)
>  {
>  	struct irq_desc *desc = irq_to_desc(d->irq);
>  
> -	if (!gic_supports_nmi())
> +	if (!gic_supports_pseudo_nmi())
>  		return -EINVAL;
>  
>  	if (gic_peek_irq(d, GICD_ISENABLER)) {
> @@ -626,7 +626,7 @@ static void gic_irq_nmi_teardown(struct irq_data *d)
>  {
>  	struct irq_desc *desc = irq_to_desc(d->irq);
>  
> -	if (WARN_ON(!gic_supports_nmi()))
> +	if (WARN_ON(!gic_supports_pseudo_nmi()))
>  		return;
>  
>  	if (gic_peek_irq(d, GICD_ISENABLER)) {
> @@ -804,7 +804,7 @@ static inline void gic_complete_ack(u32 irqnr)
>  
>  static bool gic_rpr_is_nmi_prio(void)
>  {
> -	if (!gic_supports_nmi())
> +	if (!gic_supports_pseudo_nmi())
>  		return false;
>  
>  	return unlikely(gic_read_rpr() == GICV3_PRIO_NMI);
> @@ -911,7 +911,7 @@ static void __gic_handle_irq_from_irqsoff(struct pt_regs *regs)
>  
>  static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
>  {
> -	if (unlikely(gic_supports_nmi() && !interrupts_enabled(regs)))
> +	if (unlikely(gic_supports_pseudo_nmi() && !interrupts_enabled(regs)))
>  		__gic_handle_irq_from_irqsoff(regs);
>  	else
>  		__gic_handle_irq_from_irqson(regs);
> @@ -1162,7 +1162,7 @@ static void gic_cpu_sys_reg_init(void)
>  	/* Set priority mask register */
>  	if (!gic_prio_masking_enabled()) {
>  		write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
> -	} else if (gic_supports_nmi()) {
> +	} else if (gic_supports_pseudo_nmi()) {
>  		/*
>  		 * Check that all CPUs use the same priority space.
>  		 *
> @@ -1955,15 +1955,15 @@ static const struct gic_quirk gic_quirks[] = {
>  	}
>  };
>  
> -static void gic_enable_nmi_support(void)
> +static void gic_enable_pseudo_nmi(void)
>  {
> -	if (!gic_prio_masking_enabled() || nmi_support_forbidden)
> +	if (!gic_prio_masking_enabled() || pseudo_nmi_support_forbidden)
>  		return;
>  
>  	pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n",
>  		gic_has_relaxed_pmr_sync() ? "relaxed" : "forced");
>  
> -	static_branch_enable(&supports_pseudo_nmis);
> +	static_branch_enable(&supports_pseudo_nmi);
>  
>  	if (static_branch_likely(&supports_deactivate_key))
>  		gic_eoimode1_chip.flags |= IRQCHIP_SUPPORTS_NMI;
> @@ -2047,7 +2047,7 @@ static int __init gic_init_bases(phys_addr_t dist_phys_base,
>  	gic_prio_init();
>  	gic_dist_init();
>  	gic_cpu_init();
> -	gic_enable_nmi_support();
> +	gic_enable_pseudo_nmi();
>  	gic_smp_init();
>  	gic_cpu_pm_init();
>