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From: Richard Henderson <richard.henderson@linaro.org>
To: Ilya Leoshkevich <iii@linux.ibm.com>, qemu-devel@nongnu.org
Cc: laurent@vivier.eu, alex.bennee@linaro.org
Subject: Re: [PATCH for-7.2 14/21] accel/tcg: Hoist get_page_addr_code out of tb_lookup
Date: Tue, 16 Aug 2022 20:42:46 -0500	[thread overview]
Message-ID: <a67bc498-5155-cc40-9640-81db22b2b37a@linaro.org> (raw)
In-Reply-To: <15f8efa3aae897569383305155315d03ee5b70e3.camel@linux.ibm.com>

On 8/16/22 18:43, Ilya Leoshkevich wrote:
> On Fri, 2022-08-12 at 11:07 -0700, Richard Henderson wrote:
>> We will want to re-use the result of get_page_addr_code
>> beyond the scope of tb_lookup.
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>   accel/tcg/cpu-exec.c | 34 ++++++++++++++++++++++++----------
>>   1 file changed, 24 insertions(+), 10 deletions(-)
>>
>> diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
>> index a9b7053274..889355b341 100644
>> --- a/accel/tcg/cpu-exec.c
>> +++ b/accel/tcg/cpu-exec.c
>> @@ -209,13 +209,12 @@ static bool tb_lookup_cmp(const void *p, const
>> void *d)
>>   }
>>   
>>   /* Might cause an exception, so have a longjmp destination ready */
>> -static TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
>> -                                   target_ulong cs_base,
>> +static TranslationBlock *tb_lookup(CPUState *cpu, tb_page_addr_t
>> phys_pc,
>> +                                   target_ulong pc, target_ulong
>> cs_base,
>>                                      uint32_t flags, uint32_t cflags)
>>   {
>>       CPUArchState *env = cpu->env_ptr;
>>       TranslationBlock *tb;
>> -    tb_page_addr_t phys_pc;
>>       struct tb_desc desc;
>>       uint32_t jmp_hash, tb_hash;
>>   
>> @@ -240,11 +239,8 @@ static TranslationBlock *tb_lookup(CPUState
>> *cpu, target_ulong pc,
>>       desc.cflags = cflags;
>>       desc.trace_vcpu_dstate = *cpu->trace_dstate;
>>       desc.pc = pc;
>> -    phys_pc = get_page_addr_code(desc.env, pc);
>> -    if (phys_pc == -1) {
>> -        return NULL;
>> -    }
>>       desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
>> +
>>       tb_hash = tb_hash_func(phys_pc, pc, flags, cflags, *cpu-
>>> trace_dstate);
>>       tb = qht_lookup_custom(&tb_ctx.htable, &desc, tb_hash,
>> tb_lookup_cmp);
>>       if (tb == NULL) {
>> @@ -371,6 +367,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState
>> *env)
>>       TranslationBlock *tb;
>>       target_ulong cs_base, pc;
>>       uint32_t flags, cflags;
>> +    tb_page_addr_t phys_pc;
>>   
>>       cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
>>   
>> @@ -379,7 +376,12 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState
>> *env)
>>           cpu_loop_exit(cpu);
>>       }
>>   
>> -    tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
>> +    phys_pc = get_page_addr_code(env, pc);
>> +    if (phys_pc == -1) {
>> +        return tcg_code_gen_epilogue;
>> +    }
>> +
>> +    tb = tb_lookup(cpu, phys_pc, pc, cs_base, flags, cflags);
>>       if (tb == NULL) {
>>           return tcg_code_gen_epilogue;
>>       }
>> @@ -482,6 +484,7 @@ void cpu_exec_step_atomic(CPUState *cpu)
>>       TranslationBlock *tb;
>>       target_ulong cs_base, pc;
>>       uint32_t flags, cflags;
>> +    tb_page_addr_t phys_pc;
>>       int tb_exit;
>>   
>>       if (sigsetjmp(cpu->jmp_env, 0) == 0) {
>> @@ -504,7 +507,12 @@ void cpu_exec_step_atomic(CPUState *cpu)
>>            * Any breakpoint for this insn will have been recognized
>> earlier.
>>            */
>>   
>> -        tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
>> +        phys_pc = get_page_addr_code(env, pc);
>> +        if (phys_pc == -1) {
>> +            tb = NULL;
>> +        } else {
>> +            tb = tb_lookup(cpu, phys_pc, pc, cs_base, flags,
>> cflags);
>> +        }
>>           if (tb == NULL) {
>>               mmap_lock();
>>               tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
>> @@ -949,6 +957,7 @@ int cpu_exec(CPUState *cpu)
>>               TranslationBlock *tb;
>>               target_ulong cs_base, pc;
>>               uint32_t flags, cflags;
>> +            tb_page_addr_t phys_pc;
>>   
>>               cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base,
>> &flags);
>>   
>> @@ -970,7 +979,12 @@ int cpu_exec(CPUState *cpu)
>>                   break;
>>               }
>>   
>> -            tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
>> +            phys_pc = get_page_addr_code(cpu->env_ptr, pc);
>> +            if (phys_pc == -1) {
>> +                tb = NULL;
>> +            } else {
>> +                tb = tb_lookup(cpu, phys_pc, pc, cs_base, flags,
>> cflags);
>> +            }
>>               if (tb == NULL) {
>>                   mmap_lock();
>>                   tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
> 
> This patch did not make it into v2, but having get_page_addr_code()
> before tb_lookup() in helper_lookup_tb_ptr() helped raise the exception
> when trying to execute a no-longer-executable TB.
> 
> Was it dropped for performance reasons?

Ah, yes.  I dropped it because I ran into some regression, and started minimizing the 
tree.  Because of the extra lock that needed to be held (next patch, also dropped), I 
couldn't prove this actually helped.

I think the bit that's causing your user-only failure at the moment is the jump cache. 
This patch hoisted the page table check before the jmp_cache.  For system, cputlb.c takes 
care of flushing the jump cache with page table changes; we still don't have anything in 
user-only that takes care of that.


r~



  reply	other threads:[~2022-08-17  1:44 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-12 18:07 [PATCH for-7.2 00/21] accel/tcg: minimize tlb lookups during translate + user-only PROT_EXEC fixes Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 01/21] linux-user/arm: Mark the commpage executable Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 02/21] linux-user/hppa: Allocate page zero as a commpage Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 03/21] linux-user/x86_64: Allocate vsyscall page " Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 04/21] linux-user: Honor PT_GNU_STACK Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 05/21] tests/tcg/i386: Move smc_code2 to an executable section Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 06/21] accel/tcg: Remove PageDesc code_bitmap Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 07/21] accel/tcg: Use bool for page_find_alloc Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 08/21] accel/tcg: Merge tb_htable_lookup into caller Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 09/21] accel/tcg: Move qemu_ram_addr_from_host_nofail to physmem.c Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 10/21] accel/tcg: Properly implement get_page_addr_code for user-only Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 11/21] accel/tcg: Use probe_access_internal for softmmu get_page_addr_code_hostp Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 12/21] accel/tcg: Add nofault parameter to get_page_addr_code_hostp Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 13/21] accel/tcg: Unlock mmap_lock after longjmp Richard Henderson
2022-08-12 18:07 ` [PATCH for-7.2 14/21] accel/tcg: Hoist get_page_addr_code out of tb_lookup Richard Henderson
2022-08-16 23:43   ` Ilya Leoshkevich
2022-08-17  1:42     ` Richard Henderson [this message]
2022-08-17 11:08       ` Ilya Leoshkevich
2022-08-17 13:15         ` Richard Henderson
2022-08-17 13:27           ` Ilya Leoshkevich
2022-08-17 13:38             ` Richard Henderson
2022-08-17 14:07               ` Ilya Leoshkevich
2022-08-17 16:07                 ` Richard Henderson
2022-08-17 13:42         ` Richard Henderson
2022-08-12 18:08 ` [PATCH for-7.2 15/21] accel/tcg: Hoist get_page_addr_code out of tb_gen_code Richard Henderson
2022-08-12 18:08 ` [PATCH for-7.2 16/21] accel/tcg: Raise PROT_EXEC exception early Richard Henderson
2022-08-12 18:08 ` [PATCH for-7.2 17/21] accel/tcg: Introduce is_same_page() Richard Henderson
2022-08-12 18:08 ` [PATCH for-7.2 18/21] accel/tcg: Remove translator_ldsw Richard Henderson
2022-08-12 18:08 ` [PATCH for-7.2 19/21] accel/tcg: Add pc and host_pc params to gen_intermediate_code Richard Henderson
2022-08-12 18:08 ` [PATCH for-7.2 20/21] accel/tcg: Add fast path for translator_ld* Richard Henderson
2022-08-12 18:08 ` [PATCH for-7.2 21/21] accel/tcg: Use DisasContextBase in plugin_gen_tb_start Richard Henderson
2022-08-16 23:12 ` [PATCH for-7.2 00/21] accel/tcg: minimize tlb lookups during translate + user-only PROT_EXEC fixes Ilya Leoshkevich

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