Re: [PATCH v2] hw/sd/sdhci: Set reset value of interrupt registers

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 6/3/25 19:23, BALATON Zoltan wrote:
> On Mon, 3 Mar 2025, BALATON Zoltan wrote:
>> On Mon, 3 Mar 2025, Philippe Mathieu-Daudé wrote:
>>> Hi Zoltan,
>>>
>>> On 10/2/25 17:03, BALATON Zoltan wrote:
>>>> The interrupt enable registers are not reset to 0 on Freescale eSDHC
>>>> but some bits are enabled on reset. At least some U-Boot versions seem
>>>> to expect this and not initialise these registers before expecting
>>>> interrupts. Use existing vendor property for Freescale eSDHC and set
>>>> the reset value of the interrupt registers to match Freescale
>>>> documentation.
>>>>
>>>> Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
>>>> ---
>>>> v2: Restrict to e500. Adding a reset method in a subclass does not
>>>> work because the common reset function is called directly on register
>>>> write from the guest but there's already provision for vendor specific
>>>> behaviour which can be used to restrict this to Freescale SoCs.
>>>>
>>>>   hw/ppc/e500.c         | 1 +
>>>>   hw/sd/sdhci.c         | 4 ++++
>>>>   include/hw/sd/sdhci.h | 1 +
>>>>   3 files changed, 6 insertions(+)


> This patch wasn't in the pull request but I haven't seen an answer to 
> this message either so was it missed or do you have furhter comments? 
> Bernhard has a comment about naming of SDHCI_VENDOR_FSL but I think the 
> already existing IMX name is what's wrong not the one added in this 
> patch but I don't think that's really that confusing to worth further 
> effort. We still have time as this can be considered a fix but I'd like 
> this to not get forgotten so I bring it up again.

Patch queued, thanks.