From mboxrd@z Thu Jan 1 00:00:00 1970 From: Boris Ostrovsky Subject: Re: [PATCH 10/19] x86/mce: always write 0 to MSR_IA32_MCG_STATUS on Intel CPU Date: Fri, 17 Feb 2017 10:01:24 -0500 Message-ID: References: <20170217063936.13208-1-haozhong.zhang@intel.com> <20170217063936.13208-11-haozhong.zhang@intel.com> <58A6DDC9020000780013B336@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <58A6DDC9020000780013B336@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: Jan Beulich , Suravee Suthikulpanit , Haozhong Zhang Cc: Andrew Cooper , Christoph Egger , xen-devel@lists.xen.org List-Id: xen-devel@lists.xenproject.org CgpPbiAwMi8xNy8yMDE3IDA1OjI2IEFNLCBKYW4gQmV1bGljaCB3cm90ZToKPj4+PiBPbiAxNy4w Mi4xNyBhdCAwNzozOSwgPGhhb3pob25nLnpoYW5nQGludGVsLmNvbT4gd3JvdGU6Cj4+IC0tLSBh L3hlbi9hcmNoL3g4Ni9jcHUvbWNoZWNrL21jZS5jCj4+ICsrKyBiL3hlbi9hcmNoL3g4Ni9jcHUv bWNoZWNrL21jZS5jCj4+IEBAIC01MzgsNyArNTM4LDE0IEBAIHZvaWQgbWNoZWNrX2Ntbl9oYW5k bGVyKGNvbnN0IHN0cnVjdCBjcHVfdXNlcl9yZWdzICpyZWdzKQo+PiAgICAgIGdzdGF0dXMgPSBt Y2FfcmRtc3IoTVNSX0lBMzJfTUNHX1NUQVRVUyk7Cj4+ICAgICAgaWYgKChnc3RhdHVzICYgTUNH X1NUQVRVU19NQ0lQKSAhPSAwKSB7Cj4+ICAgICAgICAgIG1jZV9wcmludGsoTUNFX0NSSVRJQ0FM LCAiTUNFOiBDbGVhciBNQ0lQQCBsYXN0IHN0ZXAiKTsKPj4gLSAgICAgICAgbWNhX3dybXNyKE1T Ul9JQTMyX01DR19TVEFUVVMsIGdzdGF0dXMgJiB+TUNHX1NUQVRVU19NQ0lQKTsKPj4gKyAgICAg ICAgaWYgKCBib290X2NwdV9kYXRhLng4Nl92ZW5kb3IgPT0gWDg2X1ZFTkRPUl9JTlRFTCApCj4+ ICsgICAgICAgICAgICAvKgo+PiArICAgICAgICAgICAgICogSW50ZWwgU0RNIDM6IEFuIGF0dGVt cHQgdG8gd3JpdGUgdG8gSUEzMl9NQ0dfU1RBVFVTCj4+ICsgICAgICAgICAgICAgKiB3aXRoIGFu eSB2YWx1ZSBvdGhlciB0aGFuIDAgd291bGQgcmVzdWx0IGluICNHUC4KPj4gKyAgICAgICAgICAg ICAqLwo+PiArICAgICAgICAgICAgbWNhX3dybXNyKE1TUl9JQTMyX01DR19TVEFUVVMsIDApOwo+ PiArICAgICAgICBlbHNlCj4+ICsgICAgICAgICAgICBtY2Ffd3Jtc3IoTVNSX0lBMzJfTUNHX1NU QVRVUywgZ3N0YXR1cyAmIH5NQ0dfU1RBVFVTX01DSVApOwo+Cj4gSSB0aGluayB0aGlzIHdhbnRz IHRvIGJlIHRoZSBvdGhlciB3YXkgYXJvdW5kOiBXcml0ZSB6ZXJvIGluIHRoZQo+IGNvbW1vbiBj YXNlLCBhbmQgbWFrZSBhbiBleGNlcHRpb24gZm9yIEFNRCAoYW5kIHRoYXQgb25seSBpZgo+IG9u IEFNRCBpdCdzIHJlYWxseSB1c2VmdWwgdG8gd3JpdGUgb3RoZXIgdGhhbiBwbGFpbiB6ZXJvKS4g Qm9yaXMsCj4gU3VyYXZlZSwgY2FuIHlvdSBwcm92aWRlIHNvbWUgaW5wdXQgaGVyZSBwbGVhc2U/ CgpJIGRvbid0IHNlZSBhbnl0aGluZyBzdGF0aW5nIHRoYXQgd3JpdGluZyBub24temVybyB2YWx1 ZXMgY2FuIHJlc3VsdCBpbiAKYW4gZXhjZXB0aW9uIG9mIGFueSBzb3J0LiBCdXQgSSBhbSBvbmx5 IGdvaW5nIGJ5IHdoYXQgSSBzZWUgaW4gdGhlIApkb2N1bWVudGF0aW9uLgoKLWJvcmlzCgpfX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpYZW4tZGV2ZWwgbWFp bGluZyBsaXN0Clhlbi1kZXZlbEBsaXN0cy54ZW4ub3JnCmh0dHBzOi8vbGlzdHMueGVuLm9yZy94 ZW4tZGV2ZWwK