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Wed, 8 Jul 2026 07:15:33 -0500 Received: from [10.24.52.205] (a0512632.dhcp.ti.com [10.24.52.205]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 668CFJJj2721368; Wed, 8 Jul 2026 07:15:20 -0500 Message-ID: Date: Wed, 8 Jul 2026 17:45:18 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RESEND PATCH v2 5/5] drm/tidss: Fix sampling edge configuration To: Leonardo Costa CC: , , , , , , , , , , , , , , , , , , , , , , , References: <20251106141227.899054-6-s-jain1@ti.com> <20260702130010.1238089-1-leoreis.costa@gmail.com> Content-Language: en-US From: Swamil Jain In-Reply-To: <20260702130010.1238089-1-leoreis.costa@gmail.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D4:EE_|CH0PR10MB5162:EE_ X-MS-Office365-Filtering-Correlation-Id: d5b20705-61a0-4f29-39be-08dedcea9f6e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|7416014|36860700016|23010399003|5023799004|4143699003|56012099006|18002099003|22082099003|3023799007; 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The bridge requires data to be driven on the negative edge, and > this is also reflected by the `ipc` variable in `dispc_vp_enable()`, which is > set to `1`. > > With this patch applied, however, data is driven on the positive edge instead. > > According to SPRUIV7C, both `MAIN_CTRL_MMR_CFG0_DPI0_CLK_CTRL[8]` and > `DSS_VP1_POL_FREQ[14] IPC` should be programmed consistently. However, if we > follow the actual bit descriptions, and ignore the sentence saying that the two > programmed values should be the same, the data is driven on the requested edge. > >>>From SPRUIV7C (https://www.ti.com/lit/ug/spruiv7b/spruiv7c.pdf): > > MAIN_CTRL_MMR_CFG0_DPI0_CLK_CTRL[8] (DPI0_CLK_CTRL_DATA_CLK_INVDIS): > > Clock edge select for DPI0 data outputs > > Note that this value should be the same as the programmed value of > DSS_POL_FREQ[14] IPC. > > Reset Source: mod_por_rst_n > > 0 DATA and DE are driven on the falling edge of clk > 1 DATA and DE are driven on the rising edge of clk > > > DSS_VP1_POL_FREQ[14] (IPC) > > Invert pixel clock > > To set data to pixel clock relationship, CTRL_MMR_DPI0_CLK_CTRL[8] > DPI0_CLK_CTRL_DATA_CLK_INVDIS setting should be the same as the [14] > IPC setting. > > 0 Data is driven on the LCD data lines on the rising-edge of the pixel clock > 1 Data is driven on the LCD data lines on the falling-edge of the pixel clock > > So, the proposed fix to this patch is: > > ```diff > - regmap_update_bits(dispc->clk_ctrl, 0, 0x100, ipc ? 0x100 : 0x000); > + regmap_update_bits(dispc->clk_ctrl, 0, 0x100, ipc ? 0x000 : 0x100); > ``` > Thanks for the suggestion, Tomi is trying to fix this issue, please have a look: https://lore.kernel.org/all/20260529-beagley-ai-display-v3-9-7fefdc5d1adf@ideasonboard.com/ Regards, Swamil. > Reverting the patch also makes the Toshiba bridge work correctly again. > However, we can confirm that the patch is needed, otherwise only the > positive-edge case (our case) works correctly. > > In other words, the two registers need to match semantically, not numerically. > > Please ignore the previous email I sent: > https://lore.kernel.org/all/20260702104817.1219078-1-leoreis.costa@gmail.com/ > I hadn't seen this more recent thread at the time. >