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([2a01:e0a:280:24f0:9db0:474c:ff43:9f5c]) by smtp.gmail.com with ESMTPSA id lx13-20020a0562145f0d00b00685be94b4d2sm2162598qvb.18.2024.01.22.06.19.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Jan 2024 06:20:00 -0800 (PST) Message-ID: Date: Mon, 22 Jan 2024 15:19:56 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/5] buses: switch to 3-phase-reset Content-Language: en-US To: Peter Xu , Peter Maydell Cc: qemu-devel@nongnu.org, "Maciej S. Szmigiero" , Mark Cave-Ayland , "Michael S. Tsirkin" , Marcel Apfelbaum , Halil Pasic , Christian Borntraeger , Eric Farman , =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , Alex Williamson References: <20240119163512.3810301-1-peter.maydell@linaro.org> From: =?UTF-8?Q?C=C3=A9dric_Le_Goater?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=clg@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -33 X-Spam_score: -3.4 X-Spam_bar: --- X-Spam_report: (-3.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.289, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hello, On 1/22/24 03:06, Peter Xu wrote: > Hi, Peter, > > On Fri, Jan 19, 2024 at 04:35:07PM +0000, Peter Maydell wrote: >> I wrote this ages ago and recently picked it back up because of a >> recent PCI related reset ordering problem noted by Peter Xu. I'm not >> sure if this patchset is necessary as a part of fixing that ordering >> problem (it might even be possible now to have the intel_iommu device >> use 3-phase reset and put the relevant parts of its reset into the >> 'exit' phase), but either way we really ought to do this cleanup >> to reduce the amount of legacy/transitional handling we have. > > The VFIO issue I was working on may not directly benefit from this series > iiuc, as it's more of an special ordering on both (1) VFIO special case > reset path using qemu_register_reset(), and (2) VT-d device is not put at > the right place in the QOM hierachy [1]. > > Said that, thanks a lot for posting the patches; they all look reasonable > and good cleanups to the reset infrastructure, afaict. Yes. I took the series in my vfio testing environment (x86_64 and s390x) and didn't see any issue. I will keep it for further testing. Thanks, C.