Re: [PATCH v2 13/14] target/riscv: Clear virtualization mode on reset

[TianCheng TANG <lyndra@linux.alibaba.com>]

在 2026/9/26 00:45, Daniel Henrique Barboza 写道:
>
>
> On 9/10/2026 11:39 AM, TANG Tiancheng wrote:
>> Reset enters M-mode without clearing virt_enabled, leaving an invalid
>> M-mode, V=1 state after a reset from virtual mode. Clear virt_enabled
>> alongside the privilege reset.
>>
>
> This one is quite old.
>
> Fixes: dc5bd18fa5 ("RISC-V CPU Core Definition")
>
>
Hi Daniel,

Thanks. I traced the virtualization state back to:

Fixes: ef6bb7b62682 ("target/riscv: Add the virtulisation mode")

That commit introduced env->virt and its helpers without resetting
the new state. dc5bd18fa5 predates the virtualization state, so I
think ef6bb7b62682 is a more precise reference.

Thanks,
Tiancheng

>
>> Signed-off-by: TANG Tiancheng <lyndra@linux.alibaba.com>
>> ---
>
> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
>
>
>
>>   target/riscv/cpu.c | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
>> index 
>> 5fff9d745e9b36d9cbd30f166ec91b5165e5f497..f60d7cca1e2f0008b09b1055c5cdeed3ec4ad1d3 
>> 100644
>> --- a/target/riscv/cpu.c
>> +++ b/target/riscv/cpu.c
>> @@ -980,6 +980,7 @@ static void riscv_cpu_reset_hold(Object *obj, 
>> ResetType type)
>>   #ifndef CONFIG_USER_ONLY
>>       env->misa_mxl = mcc->def->misa_mxl_max;
>>       env->priv = PRV_M;
>> +    env->virt_enabled = false;
>>       env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
>>       if (env->misa_mxl > MXL_RV32) {
>>           /*
>>