From: Zhao Liu <zhao1.liu@intel.com>
To: Dapeng Mi <dapeng1.mi@linux.intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Sean Christopherson <seanjc@google.com>,
qemu-devel@nongnu.org, kvm@vger.kernel.org,
Zide Chen <zide.chen@intel.com>,
Xiaoyao Li <xiaoyao.li@intel.com>,
Dongli Zhang <dongli.zhang@oracle.com>,
Mingwei Zhang <mizhang@google.com>,
Das Sandipan <Sandipan.Das@amd.com>,
Shukla Manali <Manali.Shukla@amd.com>,
Dapeng Mi <dapeng1.mi@intel.com>
Subject: Re: [PATCH 3/3] target/i386: Support VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL
Date: Sun, 27 Apr 2025 16:54:48 +0800 [thread overview]
Message-ID: <aA3w2PiRuNOMKwdM@intel.com> (raw)
In-Reply-To: <20250324123712.34096-4-dapeng1.mi@linux.intel.com>
> @@ -4212,7 +4213,8 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
> VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
> VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
> - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
> + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER |
> + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL,
> .features[FEAT_VMX_MISC] =
> MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
> MSR_VMX_MISC_VMWRITE_VMEXIT,
> @@ -4368,7 +4370,8 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
> VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
> VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
> - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
> + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER |
> + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL,
> .features[FEAT_VMX_MISC] =
> MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
> MSR_VMX_MISC_VMWRITE_VMEXIT,
> @@ -4511,7 +4514,8 @@ static const X86CPUDefinition builtin_x86_defs[] = {
> VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
> VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT |
> VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
> - VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
> + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER |
> + VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL,
> .features[FEAT_VMX_MISC] =
> MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT |
> MSR_VMX_MISC_VMWRITE_VMEXIT,
Instead of modifying SPR's CPU model directly, we should introduce a new
version (SapphireRapids-v4), like Skylake-Server-v4 enables
"vmx-eptp-switching".
next prev parent reply other threads:[~2025-04-27 8:33 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-24 12:37 [PATCH 0/3] Enable x86 mediated vPMU Dapeng Mi
2025-03-24 12:37 ` [PATCH 1/3] kvm: Introduce kvm_arch_pre_create_vcpu() Dapeng Mi
2025-03-24 12:37 ` [PATCH 2/3] target/i386: Call KVM_CAP_PMU_CAPABILITY iotcl to enable/disable PMU Dapeng Mi
2025-03-26 6:46 ` Dongli Zhang
2025-03-27 0:44 ` Mi, Dapeng
2025-03-27 2:15 ` Mingwei Zhang
2025-03-27 3:47 ` Mi, Dapeng
2025-03-24 12:37 ` [PATCH 3/3] target/i386: Support VMX_VM_EXIT_SAVE_IA32_PERF_GLOBAL_CTRL Dapeng Mi
2025-04-27 8:54 ` Zhao Liu [this message]
2025-04-27 9:42 ` Mi, Dapeng
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