Re: [PATCH v1 15/16] iommu/tegra241-cmdqv: Add user-space use support

[Nicolin Chen <nicolinc@nvidia.com>]

On Wed, Apr 23, 2025 at 08:13:33PM -0300, Jason Gunthorpe wrote:
> On Wed, Apr 23, 2025 at 11:31:29AM -0700, Nicolin Chen wrote:
> 
> > > It also needs to act like a mdev and lock down the part of the IOAS
> > > that provides that memory so the pin can't be released and UAF things.
> > 
> > If I capture this correctly, the GPA->PA mapping is already done
> > at the IOAS level for the S2 HWPT/domain, i.e. pages are already
> > pinned. So we just need to a pair of for-driver APIs to validate
> > the contiguity and refcount pages calling iopt_area_add_access().
> 
> Yes, adding an access is the key thing, the access will give you a
> page list which you can validate, but it also provides a way to
> synchronize if a hostile userspace does an unmap.

The new APIs are very like iommufd_access_pin/unpin_pages(). But
to reduce the amount of code that we have to share with driver.o,
I added a smaller iopt_area_get/put_access() that gets an access
and increases/decreases the refcounts only.

Yet, this still inevitably doubled (-ish) the size of driver.o:
   text	   data	    bss	    dec	    hex	filename
   4429	    296	      0	   4725	   1275	drivers/iommu/iommufd/driver.o
   text	   data	    bss	    dec	    hex	filename
   8430	    783	      0	   9213	   23fd	drivers/iommu/iommufd/driver.o

Meanwhile, I am thinking if we could use the known S2 domain to
translate the GPAs to PAs for the contiguity test, which feels a
little cleaner to do in an IOMMU driver v.s. with a page list?

Thanks
Nicolin