Re: [PATCH 3/4] LoongArch: dts: Add initial SoC devicetree for Loongson 2K0300

[Yao Zi <ziyao@disroot.org>]

On Thu, May 01, 2025 at 12:55:04PM +0200, Krzysztof Kozlowski wrote:
> On 01/05/2025 06:42, Yao Zi wrote:
> > Add SoC devicetree for 2K0300 SoC, which features one LA264 dual-issue
> > core and targets embedded market. Only CPU core, legacy interrupt
> > controllers and UARTs are defined for now.
> > 
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> >  arch/loongarch/boot/dts/loongson-2k0300.dtsi | 197 +++++++++++++++++++
> >  1 file changed, 197 insertions(+)
> >  create mode 100644 arch/loongarch/boot/dts/loongson-2k0300.dtsi
> > 
> > diff --git a/arch/loongarch/boot/dts/loongson-2k0300.dtsi b/arch/loongarch/boot/dts/loongson-2k0300.dtsi
> > new file mode 100644
> > index 000000000000..6991a368ff94
> > --- /dev/null
> > +++ b/arch/loongarch/boot/dts/loongson-2k0300.dtsi
> > @@ -0,0 +1,197 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2025 Loongson Technology Corporation Limited
> > + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > +	compatible = "loongson,ls2k0300";
> > +	#address-cells = <2>;
> > +	#size-cells = <2>;
> > +
> > +	aliases {
> > +		serial0 = &uart0;
> > +		serial1 = &uart1;
> > +		serial2 = &uart2;
> > +		serial3 = &uart3;
> > +		serial4 = &uart4;
> > +		serial5 = &uart5;
> > +		serial6 = &uart6;
> > +		serial7 = &uart7;
> > +		serial8 = &uart8;
> > +		serial9 = &uart9;
> 
> 
> UARTs depend on connectors, so these are board-level aliases.
> 
> 
> > +	};
> > +
> > +	cpus {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		cpu0: cpu@0 {
> > +			compatible = "loongson,la264";
> > +			reg = <0>;
> > +			device_type = "cpu";
> > +			clocks = <&cpu_clk>;
> > +		};
> > +
> > +	};
> > +
> > +	cpuintc: interrupt-controller {
> > +		compatible = "loongson,cpu-interrupt-controller";
> > +		interrupt-controller;
> > +		#interrupt-cells = <1>;
> > +	};
> > +
> > +	cpu_clk: clock-1000m {
> > +		compatible = "fixed-clock";
> > +		clock-frequency = <1000000000>;
> > +		#clock-cells = <0>;
> > +	};
> > +
> > +	soc {
> > +		compatible = "simple-bus";
> > +		#address-cells = <2>;
> > +		#size-cells = <2>;
> > +		ranges = <0x00 0x10000000 0x00 0x10000000 0x0 0x10000000>,
> > +			 <0x00 0x02000000 0x00 0x02000000 0x0 0x04000000>,
> > +			 <0x00 0x40000000 0x00 0x40000000 0x0 0x40000000>;
> > +
> > +		liointc0: interrupt-controller@16001400{
> 
> Missing space, {
> 
> > +			compatible = "loongson,liointc-2.0";
> > +			reg = <0x0 0x16001400 0x0 0x40>,
> > +			      <0x0 0x16001040 0x0 0x8>;
> > +			reg-names = "main", "isr0";
> > +
> > +			interrupt-controller;
> > +			#interrupt-cells = <2>;
> > +
> > +			interrupt-parent = <&cpuintc>;
> > +			interrupts = <2>;
> > +			interrupt-names = "int0";
> > +
> > +			loongson,parent_int_map = <0xffffffff>, /* int0 */
> > +						  <0x00000000>, /* int1 */
> > +						  <0x00000000>, /* int2 */
> > +						  <0x00000000>; /* int3 */
> > +		};
> > +
> 
> 
> 
> Best regards,
> Krzysztof
> 

Thanks for finding the issues, will fix all of them in v2.

Thanks,
Yao Zi