Re: [PATCH] perf/x86/intel: KVM: Mask PEBS_ENABLE loaded for guest with vCPU's value.

[Sean Christopherson <seanjc@google.com>]

On Sun, Apr 27, 2025, Dapeng Mi wrote:
> On 4/26/2025 8:13 AM, Sean Christopherson wrote:
> Currently we have this Sean's fix, only the guest PEBS event bits of
> IA32_PEBS_ENABLE MSR are enabled in non-root mode, suppose we can simply
> change global_ctrl guest value calculation to this.
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 09d2d66c9f21..5bc56bb616ec 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -4342,9 +4342,12 @@ static struct perf_guest_switch_msr
> *intel_guest_get_msrs(int *nr, void *data)
>         arr[global_ctrl] = (struct perf_guest_switch_msr){
>                 .msr = MSR_CORE_PERF_GLOBAL_CTRL,
>                 .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
> -               .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask & ~pebs_mask,
> +               .guest = intel_ctrl & ~cpuc->intel_ctrl_host_mask,
>         };

Hmm, that's not as clear cut.  PEBS needs to be disabled because leaving it enabled
will crash the guest.  For the counter itself, unless leaving it enabled breaks
perf and/or degrades the sampling, I don't think there's an obvious right/wrong
approach.

E.g. if the host wants to profile host and guest, then keeping the count running
while the guest is active might be a good thing.  It's still far, far from
perfect, as a counter that overflows when the guest is active won't generate a
PEBS record, but without digging further, it's not obvious that even that flaw
is overall worse than always disabling the counter.