All of lore.kernel.org
 help / color / mirror / Atom feed
From: Lorenzo Pieralisi <lpieralisi@kernel.org>
To: Marc Zyngier <maz@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
	Sascha Bischoff <sascha.bischoff@arm.com>,
	Timothy Hayes <timothy.hayes@arm.com>,
	"Liam R. Howlett" <Liam.Howlett@oracle.com>,
	Mark Rutland <mark.rutland@arm.com>,
	Jiri Slaby <jirislaby@kernel.org>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v3 20/25] irqchip/gic-v5: Add GICv5 PPI support
Date: Thu, 8 May 2025 12:44:45 +0200	[thread overview]
Message-ID: <aByLHdktOLUk8HCN@lpieralisi> (raw)
In-Reply-To: <864ixvh4ss.wl-maz@kernel.org>

On Thu, May 08, 2025 at 09:42:27AM +0100, Marc Zyngier wrote:
> On Thu, 08 May 2025 08:42:41 +0100,
> Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
> > 
> > On Wed, May 07, 2025 at 04:57:07PM +0200, Thomas Gleixner wrote:
> > > On Wed, May 07 2025 at 14:52, Marc Zyngier wrote:
> > > > On Wed, 07 May 2025 14:42:42 +0100,
> > > > Thomas Gleixner <tglx@linutronix.de> wrote:
> > > >> 
> > > >> On Wed, May 07 2025 at 10:14, Marc Zyngier wrote:
> > > >> > On Tue, 06 May 2025 16:00:31 +0100,
> > > >> > Thomas Gleixner <tglx@linutronix.de> wrote:
> > > >> >> 
> > > >> >> How does this test distinguish between LEVEL_LOW and LEVEL_HIGH? It only
> > > >> >> tests for level, no? So the test is interesting at best ...
> > > >> >
> > > >> > There is no distinction between HIGH and LOW, RISING and FALLING, in
> > > >> > any revision of the GIC architecture.
> > > >> 
> > > >> Then pretending that there is a set_type() functionality is pretty daft
> > > >
> > > > You still need to distinguish between level and edge when this is
> > > > programmable (which is the case for a subset of the PPIs).
> > > 
> > > Fair enough, but can we please add a comment to this function which
> > > explains this oddity.
> > 
> > Getting back to this, I would need your/Marc's input on this.
> > 
> > I think it is fair to remove the irq_set_type() irqchip callback for
> > GICv5 PPIs because there is nothing to set, as I said handling mode
> > for these IRQs is fixed. I don't think this can cause any trouble
> > (IIUC a value within the IRQF_TRIGGER_MASK should be set on requesting
> > an IRQ to "force" the trigger to be programmed and even then core code
> > would not fail if the irq_set_type() irqchip callback is not
> > implemented).
> > 
> > I am thinking about *existing* drivers that request GICv3 PPIs with
> > values in IRQF_TRIGGER_MASK set (are there any ? Don't think so but you
> > know better than I do), when we switch over to GICv5 we would have no
> > irq_set_type() callback for PPIs but I think we are still fine, not
> > implementing irqchip.irq_set_type() is correct IMO.
> 
> Nobody seems to use a hardcoded trigger (well, there is one exception,
> but that's to paper over a firmware bug).

That's what I get if I remove the PPI irq_set_type() callback (just one
timer, removed others because they add nothing) and enable debug for
kernel/irq/manage.c (+additional printout):

 genirq: No set_type function for IRQ 70 (GICv5-PPI)
  __irq_set_trigger+0x13c/0x180
  __setup_irq+0x3d8/0x7c0
  __request_percpu_irq+0xbc/0x114
  arch_timer_register+0x84/0x140
  arch_timer_of_init+0x180/0x1d0
  timer_probe+0x74/0x124
  time_init+0x18/0x58
  start_kernel+0x198/0x384
  __primary_switched+0x88/0x90

 arch_timer: check_ppi_trigger irq 70 flags 8
 genirq: enable_percpu_irq irq 70 type 8
 genirq: No set_type function for IRQ 70 (GICv5-PPI)
  __irq_set_trigger+0x13c/0x180
  enable_percpu_irq+0x100/0x140
  arch_timer_starting_cpu+0x54/0xb8
  cpuhp_issue_call+0x254/0x3a8
  __cpuhp_setup_state_cpuslocked+0x208/0x2c8
  __cpuhp_setup_state+0x50/0x74
  arch_timer_register+0xc4/0x140
  arch_timer_of_init+0x180/0x1d0
  timer_probe+0x74/0x124
  time_init+0x18/0x58
  start_kernel+0x198/0x384
  __primary_switched+0x88/0x90

I noticed that, if the irq_set_type() function is not implemented,
we don't execute (in __irq_set_trigger()):

irq_settings_set_level(desc);
irqd_set(&desc->irq_data, IRQD_LEVEL);

which in turn means that irqd_is_level_type(&desc->irq_data) is false
for PPIs (ie arch timers, despite being level interrupts).

An immediate side effect is that they show as edge in:

/proc/interrupts

but that's just what I could notice.

Should I set them myself in PPI translate/alloc functions ?

Removing the irq_set_type() for PPIs does not seem so innocuous, it is a
bit complex to check all ramifications, please let me know if you spot
something I have missed.

> > On the other hand, given that on GICv5 PPI handling mode is fixed,
> > do you think that in the ppi_irq_domain_ops.translate() callback,
> > I should check the type the firmware provided and fail the translation
> > if it does not match the HW hardcoded value ?
> 
> Why? The fact that the firmware is wrong doesn't change the hardware
> integration. It just indicates that whoever wrote the firmware didn't
> read the documentation.
> 
> Even more, I wonder what the benefit of having that information in the
> firmware tables if the only thing that matters in the immutable HW
> view. Yes, having it in the DT/ACPI simplifies the job of the kernel
> (only one format to parse). But it is overall useless information.

Yes, that I agree but it would force firmware bindings to special case
PPIs to remove the type (#interrupt-cells and co.).

From what I read I understand I must ignore the PPI type provided by
firmware.

> > Obviously if firmware exposes the wrong type that's a firmware bug
> > but I was wondering whether it is better to fail the firmware-to-Linux
> > IRQ translation if the firmware provided type is wrong rather than carry
> > on pretending that the type is correct (I was abusing the irq_set_type()
> > callback to do just that - namely, check that the type provided by
> > firmware matches HW but I think that's the wrong place to put it).
> 
> I don't think there is anything to do. Worse case, you spit a
> pr_warn_once() and carry on.

Thanks,
Lorenzo


  reply	other threads:[~2025-05-08 10:47 UTC|newest]

Thread overview: 49+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-06 12:23 [PATCH v3 00/25] Arm GICv5: Host driver implementation Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 01/25] dt-bindings: interrupt-controller: Add Arm GICv5 Lorenzo Pieralisi
2025-05-06 19:08   ` Rob Herring
2025-05-07  8:35     ` Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 02/25] arm64/sysreg: Add GCIE field to ID_AA64PFR2_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 03/25] arm64/sysreg: Add ICC_PPI_PRIORITY<n>_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 04/25] arm64/sysreg: Add ICC_ICSR_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 05/25] arm64/sysreg: Add ICC_PPI_HMR<n>_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 06/25] arm64/sysreg: Add ICC_PPI_ENABLER<n>_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 07/25] arm64/sysreg: Add ICC_PPI_{C/S}ACTIVER<n>_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 08/25] arm64/sysreg: Add ICC_PPI_{C/S}PENDR<n>_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 09/25] arm64/sysreg: Add ICC_CR0_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 10/25] arm64/sysreg: Add ICC_PCR_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 11/25] arm64/sysreg: Add ICC_IDR0_EL1 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 12/25] arm64/sysreg: Add ICH_HFGRTR_EL2 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 13/25] arm64/sysreg: Add ICH_HFGWTR_EL2 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 14/25] arm64/sysreg: Add ICH_HFGITR_EL2 Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 15/25] arm64: Disable GICv5 read/write/instruction traps Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 16/25] arm64: cpucaps: Rename GICv3 CPU interface capability Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 17/25] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 18/25] arm64: smp: Support non-SGIs for IPIs Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 19/25] arm64: Add support for GICv5 GSB barriers Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 20/25] irqchip/gic-v5: Add GICv5 PPI support Lorenzo Pieralisi
2025-05-06 15:00   ` Thomas Gleixner
2025-05-07  8:29     ` Lorenzo Pieralisi
2025-05-07  9:14     ` Marc Zyngier
2025-05-07 13:42       ` Thomas Gleixner
2025-05-07 13:52         ` Marc Zyngier
2025-05-07 14:57           ` Thomas Gleixner
2025-05-07 15:48             ` Lorenzo Pieralisi
2025-05-08  7:42             ` Lorenzo Pieralisi
2025-05-08  8:42               ` Marc Zyngier
2025-05-08 10:44                 ` Lorenzo Pieralisi [this message]
2025-05-09  8:07                   ` Lorenzo Pieralisi
2025-05-09  8:35                     ` Lorenzo Pieralisi
2025-05-12  8:32                       ` Marc Zyngier
2025-05-12  8:27                   ` Marc Zyngier
2025-05-06 12:23 ` [PATCH v3 21/25] irqchip/gic-v5: Add GICv5 IRS/SPI support Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 22/25] irqchip/gic-v5: Add GICv5 LPI/IPI support Lorenzo Pieralisi
2025-05-06 15:07   ` Thomas Gleixner
2025-05-07  8:30     ` Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 23/25] irqchip/gic-v5: Enable GICv5 SMP booting Lorenzo Pieralisi
2025-05-06 12:23 ` [PATCH v3 24/25] irqchip/gic-v5: Add GICv5 ITS support Lorenzo Pieralisi
2025-05-09  0:47   ` kernel test robot
2025-05-06 12:23 ` [PATCH v3 25/25] arm64: Kconfig: Enable GICv5 Lorenzo Pieralisi
2025-05-06 14:05 ` [PATCH v3 00/25] Arm GICv5: Host driver implementation Marc Zyngier
2025-05-07  7:54   ` Lorenzo Pieralisi
2025-05-07  9:09     ` Marc Zyngier
2025-05-07 10:01       ` Lorenzo Pieralisi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=aByLHdktOLUk8HCN@lpieralisi \
    --to=lpieralisi@kernel.org \
    --cc=Liam.Howlett@oracle.com \
    --cc=arnd@arndb.de \
    --cc=catalin.marinas@arm.com \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=jirislaby@kernel.org \
    --cc=krzk+dt@kernel.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=maz@kernel.org \
    --cc=robh@kernel.org \
    --cc=sascha.bischoff@arm.com \
    --cc=tglx@linutronix.de \
    --cc=timothy.hayes@arm.com \
    --cc=will@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.