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From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Thierry Bultel <thierry.bultel.yh@bp.renesas.com>
Cc: thierry.bultel@linatsea.fr, linux-renesas-soc@vger.kernel.org,
	geert@linux-m68k.org, paul.barker.ct@bp.renesas.com,
	linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org
Subject: Re: [PATCH v9 06/10] serial: sh-sci: Use private port ID
Date: Wed, 21 May 2025 13:00:48 +0200	[thread overview]
Message-ID: <aC2yYDpsv7ef9IVA@shikoro> (raw)
In-Reply-To: <20250515141828.43444-7-thierry.bultel.yh@bp.renesas.com>

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On Thu, May 15, 2025 at 04:18:21PM +0200, Thierry Bultel wrote:
> New port types cannot be added in serial_core.h, which is shared with
> userspace.
> In order to support new port types, the coming new ones will have
> BIT(7) set in the id value, and in this case, uartport->type is
> set to PORT_GENERIC.
> This commit therefore changes all the places where the port type is
> read, by not relying on uartport->type but on the private
> value stored in struct sci_port.

I quite like this approach to become independent of serial_core.h by
adding a driver-local type. Because it changes only access to the
variables but not much the logic of this driver. Two high level comments
I do have:

- I'd go for bit 31 as the flag, though. It is extremly unlikely that we
  ever need a number in serial_core.h again, but if, it could likely be
  > 127

- whatever bit numer we choose, it should be hidden as a constant. My
  suggestion:

#define SCI_LOCAL_PORT_FLAG	BIT(x)

?


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  reply	other threads:[~2025-05-21 11:00 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-15 14:18 [PATCH v9 00/10] Add initial support for Renesas RZ/T2H SoC Thierry Bultel
2025-05-15 14:18 ` [PATCH v9 01/10] dt-bindings: serial: Added secondary clock for RZ/T2H RSCI Thierry Bultel
2025-05-15 15:35   ` Rob Herring (Arm)
2025-05-23  9:05   ` Geert Uytterhoeven
2025-05-15 14:18 ` [PATCH v9 02/10] dt-bindings: clock: Add cpg for the Renesas RZ/T2H SoC Thierry Bultel
2025-05-23 10:00   ` Geert Uytterhoeven
2025-05-15 14:18 ` [PATCH v9 03/10] soc: renesas: Add RZ/T2H (R9A09G077) config option Thierry Bultel
2025-05-23 10:00   ` Geert Uytterhoeven
2025-05-15 14:18 ` [PATCH v9 04/10] clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register Thierry Bultel
2025-05-23 10:01   ` Geert Uytterhoeven
2025-05-15 14:18 ` [PATCH v9 05/10] clk: renesas: Add support for R9A09G077 SoC Thierry Bultel
2025-05-23 10:01   ` Geert Uytterhoeven
2025-05-15 14:18 ` [PATCH v9 06/10] serial: sh-sci: Use private port ID Thierry Bultel
2025-05-21 11:00   ` Wolfram Sang [this message]
2025-05-23  9:45     ` Geert Uytterhoeven
2025-05-23 12:21       ` Wolfram Sang
2025-05-23 12:27         ` Thierry Bultel
2025-05-23 13:15           ` Wolfram Sang
2025-05-23  9:46   ` Geert Uytterhoeven
2025-05-23 13:17   ` Wolfram Sang
2025-05-15 14:18 ` [PATCH v9 07/10] serial: sh-sci: Add support for RZ/T2H SCI Thierry Bultel
2025-05-23  9:57   ` Geert Uytterhoeven
2025-05-15 14:18 ` [PATCH v9 08/10] arm64: dts: renesas: Add initial support for renesas RZ/T2H SoC Thierry Bultel
2025-05-15 14:18 ` [PATCH v9 09/10] arm64: dts: renesas: Add initial support for renesas RZ/T2H eval board Thierry Bultel
2025-05-15 14:18 ` [PATCH v9 10/10] arm64: defconfig: Enable Renesas RZ/T2H serial SCI Thierry Bultel

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