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From: Niklas Cassel <cassel@kernel.org>
To: Rob Herring <robh@kernel.org>
Cc: "Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Abraham I" <kishon@kernel.org>,
	dlemoal@kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: Re: [PATCH] dt-bindings: PCI: pci-ep: Add ref-clk-mode
Date: Wed, 14 May 2025 08:51:45 +0200	[thread overview]
Message-ID: <aCQ9ge1eROhh9RVE@ryzen> (raw)
In-Reply-To: <aCOAmQNWUWU55VKT@ryzen>

Rob,

On Tue, May 13, 2025 at 07:25:50PM +0200, Niklas Cassel wrote:
> On Mon, May 12, 2025 at 08:59:09AM -0500, Rob Herring wrote:
> 
> I do realize that, for boards supporting more than a single mode (Common
> Clock/SRNS/SRIS), this device tree property is basically a configuration
> option. For boards only supporting a single mode, it is actually describing
> the hardware.
> 
> E.g. Rock 5b can run in both SRNS and SRIS mode (Common Clock is not
> supported), and since this has to be configured before starting the link,
> I cannot think of a better way to control this than a device tree property.

Just to provide some additional context (although it was mentioned in the
commit log), basically what I am trying to accomplish is to replace the
vendor specific properties
"nvidia,enable-ext-refclk" (Common Clock) and "nvidia,enable-srns" (SRNS)
(the tegra SoC does not support SRIS, that is why it doesn't have a
property for that) with a generic property that can be used by all PCIe
endpoint controller drivers.

IMO, there is really no reason to have two properties for this, it is
cleaner to just have a single property which is basically an enum
(as suggested by this patch).

To bring some additional insight of how it will be used, one could grep
for nvidia,enable-ext-refclk and nvidia,enable-srns in the tree.

My plan was to get some feedback on this binding before implementing
support for SRIS in the dw-rockchip driver, but I can also modify the
tegra driver to also support this new property in V2.


Kind regards,
Niklas

  reply	other threads:[~2025-05-14  6:51 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-25  9:20 [PATCH] dt-bindings: PCI: pci-ep: Add ref-clk-mode Niklas Cassel
2025-04-30  7:05 ` Manivannan Sadhasivam
2025-04-30  7:16   ` Niklas Cassel
2025-04-30  7:53     ` Manivannan Sadhasivam
2025-05-09 18:18       ` Rob Herring
2025-05-09 19:31         ` Manivannan Sadhasivam
2025-05-10 11:04           ` Niklas Cassel
2025-05-12 13:59             ` Rob Herring
2025-05-13 17:25               ` Niklas Cassel
2025-05-14  6:51                 ` Niklas Cassel [this message]
2025-05-19 14:56                 ` Rob Herring
2025-04-30  7:18   ` Krzysztof Kozlowski

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