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Date: Mon, 19 May 2025 11:56:51 +0100
From: Catalin Marinas <catalin.marinas@arm.com>
To: D Scott Phillips <scott@os.amperecomputing.com>
Cc: James Clark <james.clark@linaro.org>, James Morse <james.morse@arm.com>,
	Joey Gouly <joey.gouly@arm.com>,
	Kevin Brodsky <kevin.brodsky@arm.com>,
	Marc Zyngier <maz@kernel.org>, Mark Brown <broonie@kernel.org>,
	Mark Rutland <mark.rutland@arm.com>,
	Oliver Upton <oliver.upton@linux.dev>,
	"Rob Herring (Arm)" <robh@kernel.org>,
	Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>,
	Shiqi Liu <shiqiliu@hust.edu.cn>, Will Deacon <will@kernel.org>,
	Yicong Yang <yangyicong@hisilicon.com>, kvmarm@lists.linux.dev,
	linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4] arm64: errata: Work around AmpereOne's erratum
 AC04_CPU_23
Message-ID: <aCsOc7VeJTJFk-x6@arm.com>
References: <20250513184514.2678288-1-scott@os.amperecomputing.com>
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In-Reply-To: <20250513184514.2678288-1-scott@os.amperecomputing.com>

On Tue, May 13, 2025 at 11:45:14AM -0700, D Scott Phillips wrote:
> On AmpereOne AC04, updates to HCR_EL2 can rarely corrupt simultaneous
> translations for data addresses initiated by load/store instructions.
> Only instruction initiated translations are vulnerable, not translations
> from prefetches for example. A DSB before the store to HCR_EL2 is
> sufficient to prevent older instructions from hitting the window for
> corruption, and an ISB after is sufficient to prevent younger
> instructions from hitting the window for corruption.
> 
> Signed-off-by: D Scott Phillips <scott@os.amperecomputing.com>
> Reviewed-by: Oliver Upton <oliver.upton@linux.dev>

For the core arm64 bits:

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

Marc, Will - any preference on how this should go in (kvm or arm64
trees)?