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Fri, 23 May 2025 11:30:46 -0700 (PDT) Received: from ghost ([2601:647:6700:64d0:bb2c:c7d9:9014:13ab]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-310f7eb53a9sm1014559a91.12.2025.05.23.11.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 11:30:45 -0700 (PDT) Date: Fri, 23 May 2025 11:30:42 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland , Andrew Jones , Deepak Gupta Subject: Re: [PATCH v8 09/14] riscv: misaligned: move emulated access uniformity check in a function Message-ID: References: <20250523101932.1594077-1-cleger@rivosinc.com> <20250523101932.1594077-10-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250523101932.1594077-10-cleger@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250523_113047_553946_63B95D3A X-CRM114-Status: GOOD ( 22.30 ) X-BeenThere: kvm-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "kvm-riscv" Errors-To: kvm-riscv-bounces+kvm-riscv=archiver.kernel.org@lists.infradead.org On Fri, May 23, 2025 at 12:19:26PM +0200, Cl=E9ment L=E9ger wrote: > Split the code that check for the uniformity of misaligned accesses > performance on all cpus from check_unaligned_access_emulated_all_cpus() > to its own function which will be used for delegation check. No > functional changes intended. > = > Signed-off-by: Cl=E9ment L=E9ger > Reviewed-by: Andrew Jones > --- > arch/riscv/kernel/traps_misaligned.c | 20 ++++++++++++++------ > 1 file changed, 14 insertions(+), 6 deletions(-) > = > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/tra= ps_misaligned.c > index f1b2af515592..7ecaa8103fe7 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -645,6 +645,18 @@ bool __init check_vector_unaligned_access_emulated_a= ll_cpus(void) > } > #endif > = > +static bool all_cpus_unaligned_scalar_access_emulated(void) > +{ > + int cpu; > + > + for_each_online_cpu(cpu) > + if (per_cpu(misaligned_access_speed, cpu) !=3D > + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) > + return false; > + > + return true; > +} This ends up wasting time when !CONFIG_RISCV_SCALAR_MISALIGNED since it will always return false in that case. Maybe there is a way to simplify the ifdefs and still have performant code, but I don't think this is a big enough problem to prevent this patch from merging. Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins > + > #ifdef CONFIG_RISCV_SCALAR_MISALIGNED > = > static bool unaligned_ctl __read_mostly; > @@ -683,8 +695,6 @@ static int cpu_online_check_unaligned_access_emulated= (unsigned int cpu) > = > bool __init check_unaligned_access_emulated_all_cpus(void) > { > - int cpu; > - > /* > * We can only support PR_UNALIGN controls if all CPUs have misaligned > * accesses emulated since tasks requesting such control can run on any > @@ -692,10 +702,8 @@ bool __init check_unaligned_access_emulated_all_cpus= (void) > */ > on_each_cpu(check_unaligned_access_emulated, NULL, 1); > = > - for_each_online_cpu(cpu) > - if (per_cpu(misaligned_access_speed, cpu) > - !=3D RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) > - return false; > + if (!all_cpus_unaligned_scalar_access_emulated()) > + return false; > = > unaligned_ctl =3D true; > return true; > -- = > 2.49.0 > = -- = kvm-riscv mailing list kvm-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kvm-riscv From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 681752989A5 for ; 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Fri, 23 May 2025 11:30:46 -0700 (PDT) Received: from ghost ([2601:647:6700:64d0:bb2c:c7d9:9014:13ab]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-310f7eb53a9sm1014559a91.12.2025.05.23.11.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 11:30:45 -0700 (PDT) Date: Fri, 23 May 2025 11:30:42 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland , Andrew Jones , Deepak Gupta Subject: Re: [PATCH v8 09/14] riscv: misaligned: move emulated access uniformity check in a function Message-ID: References: <20250523101932.1594077-1-cleger@rivosinc.com> <20250523101932.1594077-10-cleger@rivosinc.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250523101932.1594077-10-cleger@rivosinc.com> On Fri, May 23, 2025 at 12:19:26PM +0200, Clément Léger wrote: > Split the code that check for the uniformity of misaligned accesses > performance on all cpus from check_unaligned_access_emulated_all_cpus() > to its own function which will be used for delegation check. No > functional changes intended. > > Signed-off-by: Clément Léger > Reviewed-by: Andrew Jones > --- > arch/riscv/kernel/traps_misaligned.c | 20 ++++++++++++++------ > 1 file changed, 14 insertions(+), 6 deletions(-) > > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c > index f1b2af515592..7ecaa8103fe7 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -645,6 +645,18 @@ bool __init check_vector_unaligned_access_emulated_all_cpus(void) > } > #endif > > +static bool all_cpus_unaligned_scalar_access_emulated(void) > +{ > + int cpu; > + > + for_each_online_cpu(cpu) > + if (per_cpu(misaligned_access_speed, cpu) != > + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) > + return false; > + > + return true; > +} This ends up wasting time when !CONFIG_RISCV_SCALAR_MISALIGNED since it will always return false in that case. Maybe there is a way to simplify the ifdefs and still have performant code, but I don't think this is a big enough problem to prevent this patch from merging. Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins > + > #ifdef CONFIG_RISCV_SCALAR_MISALIGNED > > static bool unaligned_ctl __read_mostly; > @@ -683,8 +695,6 @@ static int cpu_online_check_unaligned_access_emulated(unsigned int cpu) > > bool __init check_unaligned_access_emulated_all_cpus(void) > { > - int cpu; > - > /* > * We can only support PR_UNALIGN controls if all CPUs have misaligned > * accesses emulated since tasks requesting such control can run on any > @@ -692,10 +702,8 @@ bool __init check_unaligned_access_emulated_all_cpus(void) > */ > on_each_cpu(check_unaligned_access_emulated, NULL, 1); > > - for_each_online_cpu(cpu) > - if (per_cpu(misaligned_access_speed, cpu) > - != RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) > - return false; > + if (!all_cpus_unaligned_scalar_access_emulated()) > + return false; > > unaligned_ctl = true; > return true; > -- > 2.49.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CDDB2C54ED1 for ; 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Fri, 23 May 2025 11:30:46 -0700 (PDT) Received: from ghost ([2601:647:6700:64d0:bb2c:c7d9:9014:13ab]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-310f7eb53a9sm1014559a91.12.2025.05.23.11.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 May 2025 11:30:45 -0700 (PDT) Date: Fri, 23 May 2025 11:30:42 -0700 From: Charlie Jenkins To: =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= Cc: Paul Walmsley , Palmer Dabbelt , Anup Patel , Atish Patra , Shuah Khan , Jonathan Corbet , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Samuel Holland , Andrew Jones , Deepak Gupta Subject: Re: [PATCH v8 09/14] riscv: misaligned: move emulated access uniformity check in a function Message-ID: References: <20250523101932.1594077-1-cleger@rivosinc.com> <20250523101932.1594077-10-cleger@rivosinc.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250523101932.1594077-10-cleger@rivosinc.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250523_113047_592223_E0AA9B67 X-CRM114-Status: GOOD ( 22.30 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org On Fri, May 23, 2025 at 12:19:26PM +0200, Cl=E9ment L=E9ger wrote: > Split the code that check for the uniformity of misaligned accesses > performance on all cpus from check_unaligned_access_emulated_all_cpus() > to its own function which will be used for delegation check. No > functional changes intended. > = > Signed-off-by: Cl=E9ment L=E9ger > Reviewed-by: Andrew Jones > --- > arch/riscv/kernel/traps_misaligned.c | 20 ++++++++++++++------ > 1 file changed, 14 insertions(+), 6 deletions(-) > = > diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/tra= ps_misaligned.c > index f1b2af515592..7ecaa8103fe7 100644 > --- a/arch/riscv/kernel/traps_misaligned.c > +++ b/arch/riscv/kernel/traps_misaligned.c > @@ -645,6 +645,18 @@ bool __init check_vector_unaligned_access_emulated_a= ll_cpus(void) > } > #endif > = > +static bool all_cpus_unaligned_scalar_access_emulated(void) > +{ > + int cpu; > + > + for_each_online_cpu(cpu) > + if (per_cpu(misaligned_access_speed, cpu) !=3D > + RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) > + return false; > + > + return true; > +} This ends up wasting time when !CONFIG_RISCV_SCALAR_MISALIGNED since it will always return false in that case. Maybe there is a way to simplify the ifdefs and still have performant code, but I don't think this is a big enough problem to prevent this patch from merging. Reviewed-by: Charlie Jenkins Tested-by: Charlie Jenkins > + > #ifdef CONFIG_RISCV_SCALAR_MISALIGNED > = > static bool unaligned_ctl __read_mostly; > @@ -683,8 +695,6 @@ static int cpu_online_check_unaligned_access_emulated= (unsigned int cpu) > = > bool __init check_unaligned_access_emulated_all_cpus(void) > { > - int cpu; > - > /* > * We can only support PR_UNALIGN controls if all CPUs have misaligned > * accesses emulated since tasks requesting such control can run on any > @@ -692,10 +702,8 @@ bool __init check_unaligned_access_emulated_all_cpus= (void) > */ > on_each_cpu(check_unaligned_access_emulated, NULL, 1); > = > - for_each_online_cpu(cpu) > - if (per_cpu(misaligned_access_speed, cpu) > - !=3D RISCV_HWPROBE_MISALIGNED_SCALAR_EMULATED) > - return false; > + if (!all_cpus_unaligned_scalar_access_emulated()) > + return false; > = > unaligned_ctl =3D true; > return true; > -- = > 2.49.0 > = _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv